Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11145594-B2
Application number	US-201916696013-A
Country	US
Kind code	B2
Filing date	Nov 26, 2019
Priority date	Jul 23, 2019
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another;
a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack;
a plurality of channel plugs vertically formed through the first stack and the second stack;
at least one dummy plug vertically formed through the second stack without passing through the first stack; and
first and second slits formed through the first stack and the second stack, wherein the at least one dummy plug is disposed in a region adjacent to the first and second slits.

2. The semiconductor device of claim 1 , wherein the plurality of channel plugs are regularly arranged to be spaced apart from each other by a predetermined distance.

3. The semiconductor device of claim 2 , wherein the at least one dummy plug is arranged in an outermost corner region of a region where the plurality of channel plugs are arranged.

4. The semiconductor device of claim 1 ,
wherein the plurality of channel plugs and the at least one dummy plug are interposed between the first and second slits.

5. The semiconductor device of claim 1 , wherein the channel plugs and the at least one dummy plug each comprise:
a gap fill film;
a channel film surrounding the gap fill film; and
a memory film surrounding the channel film.

6. The semiconductor device of claim 1 , wherein a lower portion of the at least one dummy plug is in contact with an uppermost film of the first stack.

7. A semiconductor device comprising:
a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another;
a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack;
a plurality of channel plugs vertically formed through the first stack and the second stack;
at least one dummy plug arranged in an outermost corner region of a region where the plurality of channel plugs are arranged; and
first and second slits formed through the first stack and the second stack,
wherein a length of the dummy plug is shorter than a length of the plurality of channel plugs, and
wherein the at least one dummy plug is disposed in a region adjacent to the first and second slits.

8. The semiconductor device of claim 7 , wherein the at least one dummy plug is formed through the second stack without passing through the first stack.

9. The semiconductor device of claim 7 , wherein the plurality of channel plugs are regularly arranged to be spaced apart from each other by a predetermined distance.

10. The semiconductor device of claim 7 , wherein the plurality of channel plugs and the at least one dummy plug are interposed between the first and second slits.

11. The semiconductor device of claim 7 , wherein the channel plugs and the at least one dummy plug each comprise:
a gap fill film;
a channel film surrounding the gap fill film; and
a memory film surrounding the channel film.

12. The semiconductor device of claim 7 , wherein a lower portion of the at least one dummy plug is in contact with an uppermost film of the first stack.

13. A semiconductor device comprising:
interlayer insulating films and word line films which are alternately stacked with one another;
a plurality of channel plugs formed through the interlayer insulating films and the word line films;
at least one dummy plug arranged in an outermost corner region of a region where the plurality of channel plugs are arranged; and
first and second slits formed through the interlayer insulating films and the word line films,
wherein the dummy plug passes through at least one interlayer insulating film of the interlayer insulating films and at least one word line film of the word line films, and
wherein the at least one dummy plug is disposed in a region adjacent to the first and second slits.

14. A method of manufacturing a semiconductor device, the method comprising:
forming a first stack;
forming a plurality of first channel holes passing through the first stack;
filling the plurality of first channel holes with a reflective metal;
forming a second stack on the first stack;
forming a plurality of second channel holes through the second stack to expose the reflective metal and forming at least one dummy hole passing through the second stack;
removing the reflective metal;
forming channel plugs in the first channel holes and the second channel holes, and forming at least one dummy plug in the at least one dummy hole; and
forming first and second slits by etching the first stack and the second stack in a line shape such that the channel plugs and the at least one dummy plug are interposed between the first and second slits.

15. The method of claim 14 , wherein the second channel holes are regularly spaced apart from each other by a predetermined distance, and wherein the at least one dummy hole is arranged in an outermost corner region of a region where the second channel holes are arranged.

16. The method of claim 14 , wherein forming the at least one dummy hole comprises forming the at least one dummy hole so that a lower surface of the at least one dummy hole exposes an uppermost film of the first stack.

17. The method of claim 14 , wherein the at least one dummy plug is disposed adjacent to the first and second slits.

Assignees

• Sk Hynix Inc

Inventors

• Park Hae Chan
• Kim Jang Won
• Kim Jae Taek

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title