Framework for automated synthesis of secure, optimized system-on-chip architectures

Patent metadata

Field	Value
Publication number	US-2022019720-A1
Application number	US-202117375790-A
Country	US
Kind code	A1
Filing date	Jul 14, 2021
Priority date	Jul 17, 2020
Publication date	Jan 20, 2022
Grant date	—

Abstract

Systems and methods generate the design of a tiled multi-core system-on-chip (SoC). Design specification defining a multitude of cores to be used in the tiled multi-core SoC is analyzed and a multitude of subsystems based on the plurality of cores is built. The subsystems are augmented with one or more network adapters to generate the design of the tiled multi-core SoC. To achieve this, a multitude of IP blocks defined by the specification are retrieved from a design library. Design metadata associated with the IP blocks are extracted. Next, a standardized interface is generated for each of the IP blocks using the design metadata. Thereafter, a bus interface is generated for the IP blocks. Next, a tiled synthesizable register-transfer level code for the SoC design is generated in accordance with received configuration information.

First claim

1 . A computer-implemented method for generating a system-on-chip (“SoC”) design comprises:
receiving a specification of the SoC design;
retrieving a plurality of IP blocks defined by the specification from a design library;
extracting design metadata associated with the plurality of IP blocks;
generating a standardized interface for each of the plurality of IP blocks in accordance with the design metadata;
generating a bus interface for the plurality of IP blocks;
receiving configuration information for the plurality of IP blocks; and
generating a tiled synthesizable register-transfer level code for the SoC design in accordance with the configuration information.

2 . The method of claim 1 wherein said SoC further comprises a network-on-chip fabric.

3 . The method of claim 2 wherein said SoC further comprises a security policy engine configured to implement one or more security policies.

4 . The method power of claim 1 wherein said SoC comprises a plurality of test wrappers associated with the plurality of IP blocks.

5 . The method of claim 1 wherein said SoC comprises a plurality of security wrappers associated with the plurality of IP blocks.

6 . The method of claim 5 wherein said security wrappers are configured to facilitate on-the-fly enforcement of security policies by run-time monitoring and detection of signals used in the SoC.

7 . The method of claim 6 wherein said security wrappers are configured to apply obfuscation/logic-locking keys to the SoC design.

8 . The method of claim 7 wherein said SoC comprises a plurality of design-for-debug wrappers.

9 . The method of claim 1 further comprising:
optimizing the SoC design for performance.

10 . The method of claim 1 further comprising:
optimizing the SoC design for area usage.

11 . The method of claim 1 further comprising:
optimizing the SoC design for power consumption.

12 . The method of claim 1 further comprising:
wherein said bus interface is coupled to a hierarchical bus enabling communication between the plurality of IP blocks.

13 . A system comprising:
a memory storing instructions; and a processor, coupled with the memory and configured to execute the instructions, the instructions when executed causing the processor to:
receive a specification of a system-on-chip (“SoC”) design;
retrieve a plurality of IP blocks defined by the specification from a design library;
extract design metadata associated with the plurality of IP blocks;
generate a standardized interface for each of the plurality of IP blocks in accordance with the design metadata;
generate a bus interface for the plurality of IP blocks;
receive configuration information for the plurality of IP blocks; and
generate a tiled synthesizable register-transfer level code for the SoC design in accordance with the configuration information.

14 . The system of claim 13 wherein said SoC further comprises a network-on-chip fabric.

15 . The system of claim 14 wherein said SoC further comprises a security policy engine configured to implement one or more security policies.

16 . The system of claim 12 wherein said SoC comprises a plurality of test wrappers associated with the plurality of IP blocks.

17 . The system of claim 12 wherein said SoC comprises a plurality of security wrappers associated with the plurality of IP blocks.

18 . The system of claim 17 wherein said security wrappers are configured to facilitate on-the-fly enforcement of security policies by run-time monitoring and detection of signals used in the Soc.

19 . The system of claim 12 wherein said security wrappers are configured to apply obfuscation/logic-locking keys to the SoC design.

20 . The system of claim 12 wherein said SoC comprises a plurality of design-for-debug wrappers.

21 . The system of claim 12 wherein the SoC design is optimized for performance.

22 . The system of claim 12 wherein the SoC design is optimized for area usage.

23 . The system of claim 12 wherein the SoC design is optimized for power consumption.

24 . The system of claim 12 wherein said bus interface is coupled to a hierarchical bus enabling communication between the plurality of IP blocks.

Assignees

• Univ Florida

Inventors

• Bhunia Swarup
• Ray Sandip
• Deb Nath Atul Prasad

Classifications

• G06F2115/08

  Intellectual property [IP] blocks or IP cores · CPC title

• G06F2115/02

  System on chip [SoC] design · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L9/003 Primary

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title