Method to compensate for post-training insertion loss variation

Patent metadata

Field	Value
Publication number	US-2022014400-A1
Application number	US-202117485032-A
Country	US
Kind code	A1
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Jan 13, 2022
Grant date	—

Abstract

Methods and apparatus to compensate for post-training insertion loss variation. Receiver Physical Layer (PHY) circuitry for each receive lane in a link comprising a chain of equalizer components including a Variable Gain Amplifier (VGA). In conjunction with initial link training, the VGA gain is set based on an initial temperature. During link training, one or more of the equalizer components are adjusted to obtain link convergence, followed by transitioning to a “link up” phase under which data transmission and reception begin. While operating in the link up phase, one or more of the equalizer components are adjusted in response to changes in interconnect insertion loss to maintain operation of the link within a link margin. The method may be implemented in various types of links including but not limited to Ethernet, PCIe, CXL, and UPI links.

First claim

What is claimed is:

1 . An apparatus configured to implement an interface for a link comprising an Input/Output (I/O) link or a communications link, comprising:
for one or more receive lanes in the link, a receiver Physical Layer (PHY) circuit block having a chain of equalizer components including a variable gain amplifier (VGA); and embedded logic configured, for the receive lane, to,
set an initial VGA gain based on at least one temperature input;
perform link training during which one or more of the equalizer components are adjusted to obtain link convergence;
following link convergence, transition to a link up phase and begin receiving data; and
while operating in the link up phase, adjust one or more of the equalizer components in response to changes in insertion loss to maintain operation of the link within a link margin.

2 . The apparatus of claim 1 , wherein the chain of equalizer components includes the VGA and a Decision Feedback Equalizer (DFE), and wherein the one or more equalizer components that are adjusted in response to changes in insertion loss include the VGA and the DFE.

3 . The apparatus of claim 1 , wherein the chain of equalization components comprises a continuous time linear equalizer (CTLE), the VGA, and a Decision Feedback Equalizer (DFE).

4 . The apparatus of claim 3 , wherein a PHY receiver circuitry block includes a comparator, and wherein during link training the CTLE is configured to search for Clock and Data Rate (CDR) lock at the comparator.

5 . The apparatus of claim 1 , wherein the apparatus comprises an Ethernet PHY configured to support at least one Ethernet standard under which each of one or more lanes has a bandwidth of at least 25 Gigabits per second.

6 . The apparatus of claim 1 , wherein the apparatus comprises an Ethernet PHY, a Peripheral Component Interconnect Express (PCIe) PHY, a Compute Express Link (CXL) PHY, an Ultra Path Interconnect (UPI) PHY, a Common Public Radio Interface (CPRI) PHY, or an Optical Interconnect Forum, Common Electrical Interface (OIF-CEI) PHY.

7 . The apparatus of claim 1 , wherein the apparatus comprises a System on a Chip (SoC), and wherein the receiver PHY circuit block for each receive lane are part of an I/O link or communication link PHY block embedded on the SoC.

8 . That apparatus of claim 1 , wherein the apparatus comprises a chip configured to be electrically coupled to a printed circuit board (PCB) and the I/O link or communications link comprises signal traces in the PCB, and wherein the apparatus is configured to increase or attenuate signal gain to address changes in signal insertion loss due to changes in the PCB temperature.

9 . That apparatus of claim 1 , wherein the apparatus comprises a chip configured to be electrically coupled to a printed circuit board (PCB) and a first portion of the I/O link or communications link comprises signal traces in the PCB and a second portion of the I/O link comprises a cable, and wherein the apparatus is configured to increase or attenuate signal gain to address changes in signal insertion loss due to changes in the PCB temperature and the cable.

10 . The apparatus of claim 1 , wherein the at least one temperature input comprises a temperature of the apparatus, and the changes to the one or more temperature inputs include changes to the apparatus temperature.

11 . A method implemented in a Physical layer (PHY) chip or block for an Input/Output (I/O) link or a communications link, the PHY chip or block including a receiver Physical Layer (PHY) circuit block for one or more receive lanes in the I/O link or communication link having a chain of equalizer components including a variable gain amplifier (VGA), the method comprising:
receiving an initial temperature input; for a receive lane,
setting an initial VGA gain based on the initial temperature input;
performing link training during which one or more of the equalizer components are adjusted to obtain link convergence;
following link convergence, transitioning to a link up phase and begin receiving data; and
while operating in the link up phase, adjusting one or more of the equalizer components in response to changes in one or more temperature inputs to maintain operation of the link within a link margin.

12 . The method of claim 11 , wherein the chain of equalizer components includes the VGA and a Decision Feedback Equalizer (DFE), and wherein the one or more equalizer components that are adjusted in response to temperature changes include the VGA and the DFE.

13 . The method of claim 11 , wherein the chain of equalization components comprises a continuous time linear equalizer (CTLE), the VGA, and a Decision Feedback Equalizer (DFE), and wherein during link training the CTLE searches for Clock and Data Rate (CDR) lock at the comparator

14 . The method of claim 11 , wherein the I/O link or communications link comprises an Ethernet link in accordance with at least one Ethernet standard under which each of one or more lanes has a bandwidth of at least 25 Gigabits per second.

15 . That method of claim 11 wherein the I/O link or communications link comprises signal traces in a printed circuit board (PCB), and wherein the method is implemented to increase or attenuate signal gain to address changes in signal insertion caused by changes in the PCB temperature.

16 . The method of claim 11 , wherein the I/O link or communications link comprises a first link segment comprising signal traces in a printed circuit board (PCB) and a second link segment comprising a cable, and wherein the method is implemented to increase or attenuate signal gain to address changes in signal insertion loss caused by changes in the temperature of the PCB and the cable.

17 . A compute platform, comprising:
a printed circuit board (PCB) a System on a Chip, electrically coupled to the PCB, including a one or more processors having a plurality of processor cores and a link interface including a Physical Layer (PHY) block; one of a link partner component, a network port, or network module electrically coupled to the PCB; and a link coupled between the PHY block and the link partner component, network port, or network module, the link comprising a plurality of traces formed in the PCB, wherein the PHY block is configured to perform link training at an initial temperature and increase or attenuate signal gain for the link in response to changes in an input temperature measurement of the SoC or PCB to address changes in signal insertion loss caused by changes in the temperature of the PCB.

18 . The compute platform of claim 17 , wherein the PHY block comprises:
for each of one or more receive lanes in the link, a receiver Physical Layer (PHY) circuit block having a chain of equalizer components including a variable gain amplifier (VGA); and embedded logic configured, for each receive lane, to,
set an initial VGA gain based on an initial temperature measurement;
perform link training during which one or more of the equalizer components are adjusted to obtain link convergence;
following link convergence, transition to a link up phase and begin receiving data; and
while operating in the link up phase, adjust one or more of the equalizer components in response to changes in one or more temperature inputs to maintain operation of the link within a link margin.

19 . The compute platform of claim 18 , wherein the chain of equalizer components includes the VGA and a Decision Feedback Equalizer (DFE), and wherein the one or more equalizer components t

Assignees

• Intel Corp

Inventors

• Hadar Yaniv
• Perry Golan
• Lillie Kevan A
• Hirata Kenji

Classifications

• H05K1/0243

  Printed circuits associated with mounted high frequency components · CPC title

• H04L25/03885

  adaptive · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title