Semiconductor device having buried bias pads

Patent metadata

Field	Value
Publication number	US-2022013542-A1
Application number	US-202016936030-A
Country	US
Kind code	A1
Filing date	Jul 22, 2020
Priority date	Jul 7, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

An integrated circuit includes a bias pad within a buried oxide layer. A layer of semiconductor material is over the buried oxide layer. The layer of semiconductor material includes a doped regions for a transistor. An inter layer dielectric (ILD) material covers the layer of semiconductor material and a gate electrode for the transistor. The integrated circuit includes one or more bias contacts extending through the ILD material within an isolation region in the layer of semiconductor material. Bias contacts electrically connect to the first bias pad. The isolation structure insulates the one or more bias contacts from the doped regions of the transistor within the layer of semiconductor material. The one or more bias contacts are electrically connected to an interconnection structure of the integrated circuit which is configured to connect a voltage source to the bias pad.

First claim

1 . A semiconductor device, comprising:
a buried oxide layer over a substrate; a layer of semiconductor material over the buried oxide layer, the layer of semiconductor material including a plurality of doped regions; a transistor, wherein the transistor comprises a gate electrode and the plurality of doped regions; an isolation region in the layer of semiconductor material; an inter layer dielectric (ILD) material over the layer of semiconductor material and the gate electrode; a first bias contact extending through the ILD material and the isolation region to the buried oxide layer; and an interconnection structure electrically connected to the buried oxide layer by the first bias contact.

2 . The semiconductor device of claim 1 , further comprising a first bias pad in the buried oxide layer, wherein the first bias pad comprises an electrically conductive material.

3 . The semiconductor device of claim 2 , further comprising a second bias pad within the buried oxide layer, wherein the second bias pad is between a second transistor and the substrate, the second bias pad is electrically isolated, within the buried oxide layer, from the first bias pad by a deep trench isolation structure (DTI), wherein the second bias pad is electrically connected to the interconnection structure of the semiconductor device by a second bias contact.

4 . The semiconductor device of claim 3 , wherein, in the layer of semiconductor material, the first bias contact and the second bias contact are each separated from the layer of semiconductor material by an isolation structure in the layer of semiconductor material.

5 . The semiconductor device of claim 2 , wherein the first bias pad is electrically connected to a voltage source by the interconnection structure.

6 . The semiconductor device of claim 1 , wherein the first bias contact is isolated from the layer of semiconductor material by an isolation structure extending through the layer of semiconductor material.

7 . The semiconductor device of claim 1 , further comprising a second transistor, a bias pad below the second transistor, and a second bias contact electrically connected to the second bias pad, wherein the first bias pad has a first bias pad thickness and the second bias pad has a second bias pad thickness smaller than the first bias pad thickness.

8 . The semiconductor device of claim 1 , further comprising a second bias contact extending through the ILD material, the layer of semiconductor material, and the buried oxide layer to the substrate, and electrically connected to the interconnection structure of the semiconductor device above the ILD material.

9 . The semiconductor device of claim 8 , wherein the second bias contact is separated from the layer of semiconductor material by a deep trench isolation structure (DTI).

10 . The semiconductor device of claim 1 , further comprising a plurality of pillar-type bias contacts extending through the isolation region.

11 . The semiconductor device of claim 10 , wherein the isolation region extends around an entirety of a first transistor of an integrated circuit of the semiconductor device.

12 . The semiconductor device of claim 2 , wherein the first bias contact further comprises a bar-type bias contact extending through an isolation region of the semiconductor device and electrically connected to the first bias pad.

13 . A semiconductor device, comprising:
a buried oxide layer over a substrate; a layer of semiconductor material over the buried oxide layer; a transistor having a source well and a drain well in the layer of semiconductor material; a first bias pad within the buried oxide layer between the source well and the substrate; a second bias pad within the buried oxide layer between the drain well and the substrate; a first deep trench isolation structure (DTI) loop, wherein the first bias pad is surrounded by the first DTI loop within the buried oxide layer; and a second DTI loop surrounding the second bias pad within the buried oxide layer, the first DTI loop and the second DTI loop sharing a central DTI segment.

14 . The semiconductor device of claim 13 , having a first voltage source and a second voltage source, wherein the first bias pad is electrically connected to the first voltage source and the second bias pad is electrically connected to the second voltage source, wherein the first voltage source and the second voltage source have different voltages.

15 . The semiconductor device of claim 13 , wherein the transistor is between the central DTI segment and an inter layer dielectric (ILD) material.

16 - 20 . (canceled)

21 . A semiconductor device, comprising:
a buried oxide layer over a substrate; a layer of semiconductor material over the buried oxide layer; a transistor having a source well and a drain well in the layer of semiconductor material; a first bias pad within the buried oxide layer between the source well and the substrate; a second bias pad within the buried oxide layer between the drain well and the substrate; a first deep trench isolation structure (DTI), wherein the first bias pad is separated from the second bias pad by the first DTI; and a first bias contact extending through the semiconductor layer and partially through the buried oxide layer, wherein the first bias contact is electrically connected to the first bias pad.

22 . The semiconductor device of claim 21 , further comprising a substrate contact, wherein the substrate contact extends through the first DTI, and the substrate contact is electrically connected to the substrate.

23 . The semiconductor device of claim 22 , wherein the substrate contact is between the first bias pad and the second bias pad.

24 . The semiconductor device of claim 22 , wherein the substrate contact is electrically separated from the first bias pad and from the second bias pad by the first DTI.

25 . The semiconductor device of claim 21 , further comprising:
a third bias pad within the buried oxide layer, wherein the first bias pad is between the third bias pad and the second bias pad; and a second bias contact extending through the semiconductor layer and partially through the buried oxide layer, wherein the second bias contact is electrically connected to the third bias pad.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Tsmc China Company Ltd

Inventors

• Wu Jian
• Han Feng
• Zhang Shuai

Classifications

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title