Apparatus and method for achieving deterministic power saving state

Patent metadata

Field	Value
Publication number	US-2022011842-A1
Application number	US-202117484335-A
Country	US
Kind code	A1
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Jan 13, 2022
Grant date	—

Abstract

An apparatus comprises a first circuitry to perform, in response to a first message from an operating system, a first process to place a computer device in a first operating mode, store state information in a volatile memory of the computer device, and start a timer for a time-out period for performing the first process. First components of the computer device are in a low power state. A second circuitry to detect, after the time-out period, a failure of the first process. A third circuitry to perform, in response to the detected failure of the first process, a second process to place the computer device in a second operating mode and store state information in a non-volatile memory of the computer device. The volatile memory is operational in the first operating mode and is in a low power state in the second operating mode.

First claim

What is claimed is:

1 . An apparatus comprising:
a first circuitry to perform, in response to a first message from an operating system, a first process to place a computer device in a first operating mode, store state information in a volatile memory of the computer device, and start a timer for a time-out period for performing the first process, wherein first components of the computer device are in a low power state and the volatile memory is operational in the first operating mode; a second circuitry to detect, after expiration of the time-out period, a failure of the first process; and a third circuitry to perform, in response to the detected failure of the first process, a second process to place the computer device in a second operating mode and store state information in a non-volatile memory of the computer device, wherein the volatile memory is in a low power state in the second operating mode.

2 . The apparatus of claim 1 , wherein the first message includes instructions to place the computer device in the first operating mode and to start the timer for the time-out period for performing the first process.

3 . The apparatus of claim 1 , wherein the apparatus includes operating system instructions to send a second message to a power management unit, the message indicating that a software low power state has not been achieved.

4 . The apparatus of claim 1 , wherein the apparatus further comprises:
fourth circuitry to determine a cause for the failure of the first process.

5 . The apparatus of claim 4 , wherein the apparatus further comprises:
a power management unit to send a third message to the operating system, the third message indicating the failure of the first process.

6 . The apparatus of claim 5 , wherein the apparatus includes operating system instructions to identify one or more operations to fix the cause of the failure of the first process, the identifying of the one or more operations being based on the determined cause for the failure of the first process.

7 . The apparatus of claim 1 , wherein the apparatus further comprises:
operating system instructions to perform an operation to fix the cause of the failure of the first process; and a fifth circuitry to count instances of the operating system performing the operation to fix the cause of the failure and to determine if the count exceeds a maximum number of attempts to fix the cause of the failure.

8 . The apparatus of claim 7 , wherein the apparatus further comprises a power management unit:
to halt the first process in response to the count exceeding the maximum number of attempts to fix the cause of the failure; and to send a message to the operating system instructing the operating system to initiate the second process to place the computer device in the second operating mode.

9 . The apparatus of claim 1 , wherein the first operating mode includes an Advanced Configuration and Power Interface Modern Standby state.

10 . The apparatus of claim 1 , wherein the second operating mode includes an Advanced Configuration and Power Interface Hibernate state.

11 . The apparatus of claim 1 , wherein the state information includes at least one of operating system state information, application software state information, and processor state information.

12 . An apparatus comprising:
a first circuitry to perform, in response to a first message from an operating system, a first process to place a computer device in a first operating mode, wherein first components of the computer device are in a low power state and a volatile memory is operational in the first operating mode; a second circuitry to receive a second message from the operating system, the second message indicating that a software low power state has not been achieved and to detect, after expiration of the time-out period, a failure of the first process; and a third circuitry to perform, in response to the detected failure of the first process, a second process to place the computer device in a second operating mode and store state information in a non-volatile memory of the computer device, wherein the volatile memory is in a low power state in the second operating mode.

13 . The apparatus of claim 12 , wherein the first operating mode includes an Advanced Configuration and Power Interface Modern Standby state, and the second operating mode includes an Advanced Configuration and Power Interface Hibernate state.

14 . A system comprising:
a processor and a memory to execute an operating system;
a display device coupled to the processor, the display device to display an image based on a signal communicated to the display device; and
coupled to the processor and the memory, a power management unit to:
perform a first process to place the system in a first operating mode, store state information in a volatile memory, wherein first components of the system are in a low power state and the volatile memory is operational in the first operating mode;
detect a failure of the first process; and
perform, in response to the detected failure of the first process, a second process to place the computer device in a second operating mode and store state information in a non-volatile memory of the computer device, wherein second components of the computer device are in a low power state in the second operating mode.

15 . The system of claim 14 , wherein the system further comprises operating system instructions to send a message to a power management unit, the message indicating that a software low power state has not been achieved.

16 . The system of claim 14 , wherein the system further comprises operating system instructions to identify one or more operations to fix the cause of the failure of the first process.

17 . The system of claim 16 , wherein the one or more operations to fix the cause of the failure of the first process includes disabling a software stack or software driver.

18 . The system of claim 16 , wherein the system further comprises:
operating system instructions to perform an operation to fix the cause of the failure of the first process; and the power management unit to count instances of the operating system performing the operation to fix the cause of the failure and to determine if the count exceeds a maximum number of attempts to fix the cause of the failure.

19 . The system of claim 14 , wherein the first operating mode includes an Advanced Configuration and Power Interface S0ix state.

20 . The system of claim 14 , wherein the second operating mode includes an Advanced Configuration and Power Interface S4 state.

Assignees

• Intel Corp

Inventors

• Reddy Nagabhushan
• Gupta Abhinay
• Janarthanan Vinithra
• Krishnaswamy Santhosh Raghuram
• Rajagopal Pannerkumar
• Selvaraj Siddharth
• Shah Mihir
• Somayaji Vishwanath

Classifications

• G06F1/3225

  of memory devices · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/0757 Primary

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title