Failover for pooled memory

Patent metadata

Field	Value
Publication number	US-2022004468-A1
Application number	US-202117479267-A
Country	US
Kind code	A1
Filing date	Sep 20, 2021
Priority date	Sep 20, 2021
Publication date	Jan 6, 2022
Grant date	—

Abstract

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.

First claim

What is claimed is:

1 . An electronic apparatus, comprising:
one or more substrates; and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node; and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node.

2 . The apparatus of claim 1 , wherein the circuitry is further to:
authenticate the second instantiation of the application based on authentication information for the second instantiation of the application.

3 . The apparatus of claim 2 , wherein the circuitry is further to:
compare the authentication information for the second instantiation of the application against a trusted source to determine if the authentication of the second instantiation of the application is successful.

4 . The apparatus of claim 2 , wherein the circuitry is further to:
provide secure access information for the second instantiation of the application if the authentication is successful; and associate the first secure portion of the pooled memory with the second instantiation of the application.

5 . The apparatus of claim 4 , wherein the secure access information includes memory key information.

6 . The apparatus of claim 4 , wherein the secure access information includes an address of memory metadata that is needed to restart the second instantiation of the application.

7 . The apparatus of claim 1 , wherein the circuitry is further to:
store failover information in a second secure portion of the pooled memory; and synchronize the failover information with a host.

8 . An electronic system, comprising:
pooled memory; a controller communicatively coupled to the pooled memory to allocate a first secure portion of the pooled memory to a first instantiation of an application on a first node; and circuitry communicatively coupled to the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node.

9 . The system of claim 8 , wherein the circuitry is further to:
authenticate the second instantiation of the application based on authentication information for the second instantiation of the application.

10 . The system of claim 9 , wherein the circuitry is further to:
compare the authentication information for the second instantiation of the application against a trusted source to determine if the authentication of the second instantiation of the application is successful.

11 . The system of claim 9 , wherein the circuitry is further to:
provide secure access information for the second instantiation of the application if the authentication is successful; and associate the first secure portion of the pooled memory with the second instantiation of the application.

12 . The system of claim 11 , wherein the secure access information includes memory key information.

13 . The system of claim 11 , wherein the secure access information includes an address of memory metadata that is needed to restart the second instantiation of the application.

14 . The system of claim 8 , wherein the circuitry is further to:
store failover information in a second secure portion of the pooled memory; and synchronize the failover information with a host.

15 . A method, comprising:
allocating a first secure portion of a pooled memory to a first instantiation of an application on a first node; and providing a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node.

16 . The method of claim 15 , further comprising:
authenticating the second instantiation of the application based on authentication information for the second instantiation of the application.

17 . The method of claim 16 , further comprising:
comparing the authentication information for the second instantiation of the application against a trusted source to determine if the authentication of the second instantiation of the application is successful.

18 . The method of claim 16 , further comprising:
providing secure access information for the second instantiation of the application if the authentication is successful; and associating the first secure portion of the pooled memory with the second instantiation of the application.

19 . The method of claim 18 , wherein the secure access information includes one or more of memory key information and an address of memory metadata that is needed to restart the second instantiation of the application.

20 . The method of claim 15 , further comprising:
storing failover information in a second secure portion of the pooled memory; and synchronizing the failover information with a host.

Assignees

• Intel Corp

Inventors

• Willhalm Thomas
• Guim Bernat Francesc
• Kumar Karthik
• Gupta Rita
• Schmisseur Mark
• Ziakas Dimitrios

Classifications

• G06F21/60

  Protecting data · CPC title

• G06F11/2046

  where the redundant components share persistent storage (G06F11/2043 takes precedence) · CPC title

• G06F11/2025 Primary

  using centralised failover control functionality · CPC title

• G06F11/2043

  where the redundant components share a common memory address space · CPC title

• G06F11/1484

  involving virtual machines · CPC title