Display backplate and method for manufactring same, display panel and method for manufactuuring same, and display device

US2021407976A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2021407976-A1
Application numberUS-201916765530-A
CountryUS
Kind codeA1
Filing dateMay 31, 2019
Priority dateMay 31, 2019
Publication dateDec 30, 2021
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a display backplate includes including an array substrate and a plurality of pairs of connection structures on the array substrate, wherein the array substrate includes a plurality of thin-film transistors and a common electrode signal line, wherein at least one of the plurality of thin-film transistors is connected to one of a pair of connection structures and the common electrode signal line is connected to the other of the pair of connection structures; and an area of a first section of the connection structure is negatively correlated with a distance between the first section and a surface of the array substrate, and the first section is parallel to the surface of the array substrate.

First claim

Opening claim text (preview).

What is claimed is: 1 . A display backplate, comprising: an array substrate and a plurality of pairs of connection structures on the array substrate; wherein the array substrate comprises a plurality of thin-film transistors and a common electrode signal line, wherein at least one of the plurality of thin-film transistors is connected to one of a pair of connection structures, and the common electrode signal line is connected to the other of the pair of the connection structures; and an area of a first section of the connection structure is negatively correlated with a distance between the first section and a surface of the array substrate, and the first section is parallel to the surface of the array substrate. 2 . (canceled) 3 . The display backplate according to claim 1 , wherein the connection structure comprises a main body portion and a conductive portion, wherein the conductive portion is disposed on a surface of the main body portion distal from the array substrate; an orthographic projection of the main body portion on the array substrate falls within an orthographic projection of the conductive portion on the array substrate; the conductive portion is conformal to the surface of the main body portion distal from the array substrate; and the main body portion is made of an insulating material. 4 . The display backplate according to claim 3 , wherein a difference between thicknesses of the conductive portion at any positions is less than a predetermined value, and/or the conductive portion is made of any one or an alloy of copper and aluminum. 5 . (canceled) 6 . The display backplate according to claim 3 , wherein the main body portion comprises an organic insulating portion and an inorganic insulating portion, wherein the inorganic insulating portion is disposed between the organic insulating portion and the conductive portion. 7 . The display backplate according to claim 1 , wherein a maximum distance between the connection structure and the array substrate is in the range of between 3 micrometers and 5 micrometers, and/or the connection structure is made of any one or an alloy of copper and aluminum. 8 . The display backplate according to claim 1 , wherein the connection structure is disposed on a first side of the array substrate; the display backplate further comprises a pad disposed on a second side of the array substrate; and the second side is opposite to the first side. 9 . The display backplate according to claim 8 , further comprising a package layer, wherein the pad is disposed between the array substrate and the package layer. 10 . The display backplate according to claim 1 , further comprising a base disposed on the surface of the array substrate, wherein the base comprises recesses in one-to-one correspondence with the connection structures; an area of a second section of the recess is negatively correlated with a distance between the second section and the surface of the array substrate; the second section is parallel to the surface of the array substrate; and the connection structure is inside the corresponding recess. 11 . The display backplate according to claim 10 , wherein the base comprises a substrate, a separable layer, and a resin layer which are sequentially stacked, and the recess is disposed in the resin layer, optionally, the separable layer is made of any one of an organic resin material and GaN. 12 . The display backplate according to claim 10 , wherein the base comprises a substrate, the recess is disposed in the substrate, and the display backplate further comprises a separable layer disposed between the base and the connection structure, optionally, the separable layer is made of any one of an organic resin material and GaN. 13 . (canceled) 14 . A display device, comprising: the display backplate as defined in claim 1 , and a plurality of micro light-emitting diodes on the display backplate, wherein any one of the plurality of micro light-emitting diodes comprises a first electrode and a second electrode, wherein the first electrode and the second electrode are respectively connected to a pair of connection structures. 15 . The display device according to claim 14 , wherein a material hardness of the connection structure is greater than a material hardness of the first electrode and the second electrode. 16 . The display device according to claim 14 , wherein a surface, in contact with the connection structure, of the first electrode or the second electrode is provided with a protrusion surrounding the connection structure. 17 . A method for manufacturing a display backplate, comprising: forming a plurality of pairs of connection structures; and forming an array substrate, on which the plurality of pairs of connection structures are disposed, wherein the array substrate comprises a plurality of thin-film transistors and a common electrode signal line, wherein at least one of the plurality of thin-film transistors is connected to one of a pair of connection structures and the common electrode signal line is connected to the other of the pair of connection structures; and an area of a first section of the connection structure is negatively correlated with a distance between the first section and a surface of the array substrate, and the first section is parallel to the surface of the array substrate. 18 . The method according to claim 17 , wherein forming the plurality of pairs of connection structures comprises: providing a base; forming a recess on one side of the base, wherein an area of a second section of the recess is negatively correlated with a distance between the second section and the surface of the array substrate, and the second section is parallel to the surface of the array substrate; and forming the connection structure at least in the recess. 19 . The method according to claim 18 , wherein forming the connection structure at least in the recess comprises: forming a seed layer in the recess; and forming a metal-plated layer on the seed layer. 20 . The method according to claim 18 , wherein forming the connection structure at least in the recess comprises: sequentially forming a conductive portion and a main body portion in the recess, wherein an orthographic projection of the main body portion on the array substrate falls within an orthographic projection of the conductive portion on the array substrate; the conductive portion is conformal to a surface of the main body portion distal from the array substrate; and the main body portion is made of an insulating material. 21 . The method according to claim 18 , further comprising: removing the base. 22 . A method for manufacturing a display device, comprising: providing the display backplate as defined in claim 1 ; and transferring a plurality of micro light-emitting diodes onto the display backplate at the same time, wherein any one of the plurality of micro light-emitting diodes comprises a first electrode and a second electrode, wherein the first electrode and the second electrode are respectively connected to a pair of connection structures. 23 . The method according to claim 22 , wherein transferring the plurality of micro light-emitting diodes onto the display backplate at the same time comprises: coating the display backplate with a layer of resin material doped with a solvent; transferring the plurality of micro light-emitting diodes onto the resin material with a mass transfer

Assignees

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Classifications

  • not comprising solid metals or solid metalloids, e.g. polymers or ceramics · CPC title

  • comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

  • Cross-sectional shape, i.e. in side view · CPC title

  • Multilayered bumps, e.g. a coating on top and side surfaces of a bump core · CPC title

  • on active surfaces of flip-chip devices, e.g. underfills · CPC title

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What does patent US2021407976A1 cover?
Provided is a display backplate includes including an array substrate and a plurality of pairs of connection structures on the array substrate, wherein the array substrate includes a plurality of thin-film transistors and a common electrode signal line, wherein at least one of the plurality of thin-film transistors is connected to one of a pair of connection structures and the common electrode …
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 30 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).