Package substrate, electronic device package and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2021391284-A1
Application number	US-202016899515-A
Country	US
Kind code	A1
Filing date	Jun 11, 2020
Priority date	Jun 11, 2020
Publication date	Dec 16, 2021
Grant date	—

Abstract

The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.

First claim

1 . A package substrate, comprising:
a substrate including a first surface and a second surface opposite to the first surface; an electronic component disposed in the substrate, the electronic component comprising:
a conductive wire comprising an alignment mark section and a connection section; and
a magnetic layer partially covering the conductive wire, the magnetic layer including an upper surface adjacent to the first surface and a lower surface adjacent to the second surface, wherein the magnetic layer includes a first alignment window disposed in the upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a first recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section; and
a first conductive trace in the first recess and electrically connected to the second upper surface of the connection section of the conductive wire.

2 . The package substrate of claim 1 , further comprising a first dielectric layer disposed between the magnetic layer and the first conductive trace.

3 . The package substrate of claim 2 , wherein the first dielectric layer is disposed in the first recess of the magnetic layer, and partially surrounds the first conductive trace.

4 . The package substrate of claim 2 , wherein the substrate comprises a supporting portion defining a cavity, and the electronic component is disposed in the cavity.

5 . The package substrate of claim 4 , wherein the first dielectric layer is further disposed between edges of the electronic component and the supporting portion of the substrate.

6 . The package substrate of claim 1 , wherein the electronic component comprises a plurality of conductive wires, and the first alignment window of the magnetic layer comprises a slot continuously transversing the plurality of conductive wires and exposing the first upper surfaces of the alignment mark sections of the plurality of conductive wires.

7 . The package substrate of claim 6 , wherein the first alignment window of the magnetic layer comprises a plurality of holes disconnected from one another, and exposing the first upper surfaces of the alignment mark sections of the plurality of conductive wires, respectively.

8 . The package substrate of claim 1 , wherein a minimum width of the first alignment window is wider than a width of the conductive wire.

9 . The package substrate of claim 1 , wherein the first upper surface of the alignment mark section comprises a substantially flat surface, a concaved surface or a notched surface.

10 . The package substrate of claim 1 , wherein the second upper surface of the connection section comprises a substantially flat surface.

11 . The package substrate of claim 1 , wherein the first upper surface of the alignment mark section is lower than the second upper surface of the connection section.

12 . The package substrate of claim 1 , wherein the first alignment window partially overlaps the first recess.

13 . The package substrate of claim 1 , wherein the magnetic layer further includes a second recess disposed in the lower surface of the magnetic layer and exposing a lower surface of the connection section.

14 . The package substrate of claim 13 , wherein the second recess is aligned with the first recess.

15 . The package substrate of claim 13 , wherein the magnetic layer further includes a second alignment window disposed in the lower surface of the magnetic layer and exposing a lower surface of the alignment mark section.

16 . The package substrate of claim 13 , further comprising a second conductive trace in the second recess and electrically connected to the lower surface of the connection section of the conductive wire.

17 . The package substrate of claim 16 , further comprising a second dielectric layer disposed between the magnetic layer and the second conductive trace.

18 - 20 . (canceled)

21 . A package substrate, comprising:
a substrate including a first surface and a second surface opposite to the first surface; an electronic component embedded in the substrate, the electronic component comprising:
a magnetic layer having an upper surface and a lower surface; and
more than one linear conductive features embedded in the magnetic layer between the upper and the lower surfaces,
wherein the magnetic layer is provided with a linear trench feature that concurrently intercepts and exposes a plurality of the linear conductive features and a hole that offsets the linear trench feature and enables access to one of the linear conductive features; and
a conductive trace that extends into the hole and electrically connects the substrate and the electronic component.

22 . The package substrate of claim 21 , wherein a minimum width of the linear trench feature is wider than a width of the linear conductive feature.

23 . The package substrate of claim 21 , wherein a surface of the linear conductive feature exposed from the linear trench feature is lower than a surface of the linear conductive feature exposed from the hole.

Assignees

• Advanced Semiconductor Eng

Inventors

• Hsu Wu Chou
• Lee Chih-Cheng
• Chen Min-Yao
• Tien Hsing Kuo

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W46/301

  for alignment · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title