Diffusion barrier for semiconductor device and method

Patent metadata

Field	Value
Publication number	US-2021391275-A1
Application number	US-202016899055-A
Country	US
Kind code	A1
Filing date	Jun 11, 2020
Priority date	Jun 11, 2020
Publication date	Dec 16, 2021
Grant date	—

Abstract

A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.

First claim

What is claimed is:

1 . A method of forming a semiconductor device, the method comprising:
forming a conductive feature in a first dielectric layer; forming a second dielectric layer over the conductive feature; etching an opening through the second dielectric layer, the etching exposing a surface of the conductive feature; depositing a sacrificial layer in the opening, wherein the sacrificial layer selectively forms on the exposed surface of the conductive feature more than on surfaces of the second dielectric layer; depositing a barrier layer in the opening, wherein the barrier layer selectively forms on surfaces of the second dielectric layer over the sacrificial layer, wherein depositing the barrier layer comprises:
depositing a conductive barrier material from one or more first precursors; and
after depositing the conductive barrier material, depositing a doping metal from one or more second precursors;
removing the sacrificial layer; and depositing a conductive material to fill the opening, the conductive material contacting the conductive feature.

2 . The method of claim 1 , wherein removing the sacrificial layer comprises performing a plasma treatment process.

3 . The method of claim 2 , wherein the plasma treatment process increases the density of the barrier layer.

4 . The method of claim 1 , wherein depositing the barrier layer comprises an Atomic Layer Deposition (ALD) process.

5 . The method of claim 4 , wherein depositing the conductive barrier material comprises a Chemical Vapor Deposition (CVD) process.

6 . The method of claim 1 , wherein the sacrificial layer is formed by applying benzotriazole (BTA) on the exposed surface of the conductive feature.

7 . The method of claim 1 , wherein the doping metal is ruthenium.

8 . The method of claim 1 , wherein the conductive barrier material is tantalum nitride.

9 . The method of claim 1 , wherein depositing the conductive barrier material comprises depositing a first layer of the conductive barrier material, wherein depositing the doping metal comprises depositing a layer of the doping metal, and further comprising depositing a second layer of the conductive barrier material on the layer of the doping metal.

10 . A method comprising:
forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material comprises tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.

11 . The method of claim 10 , further comprising forming an etch stop layer over the conductive feature.

12 . The method of claim 10 , wherein the barrier layer has an atomic percentage of the transition metal in the range between 5% and 30%.

13 . The method of claim 10 , wherein the sacrificial material comprises benzotriazole (BTA).

14 . The method of claim 10 , wherein the removing of the sacrificial material comprises a thermal treatment using hydrogen (H 2 ) as a process gas.

15 . A structure comprising:
a first conductive feature in a first dielectric layer; an etch stop layer over the first conductive feature; a second dielectric layer over the etch stop layer; and a second conductive feature extending through the second dielectric layer and the etch stop layer to physically contact the first conductive feature, wherein the second conductive feature comprises:
a barrier layer extending continuously on sidewalls of the second dielectric layer and on sidewalls of the etch stop layer, wherein the barrier layer comprises a layer of a transition metal between a first layer of a metal nitride and a second layer of the metal nitride; and
a conductive filling material over the barrier layer, wherein the conductive filling material extends between the barrier layer and the first conductive feature.

16 . The structure of claim 15 , wherein the barrier layer partially covers a sidewall of the etch stop layer.

17 . The structure of claim 15 , wherein the conductive filling material physically contacts sidewalls of the etch stop layer.

18 . The structure of claim 15 , wherein the transition metal is ruthenium.

19 . The structure of claim 15 , wherein the layer of the transition metal has a thickness in the range between 1 Å and 6 Å.

20 . The structure of claim 15 , wherein a bottom of the barrier layer is vertically separated from a top of the first conductive feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Chia-Pang
• Shih Huan-Yu
• Chen Wen-Hsuan
• Tsai Cheng-Lun
• Lee Ya-Lien
• Weng Cheng-Hui
• Lin Chun-Chieh
• Su Hung-Wen
• Liu Yao-Min

Classifications

• H10P14/3216

  Nitrides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title