Method of manufacturing semiconductor devices and semiconductor devices

Patent metadata

Field	Value
Publication number	US-2021376104-A1
Application number	US-202016888548-A
Country	US
Kind code	A1
Filing date	May 29, 2020
Priority date	May 29, 2020
Publication date	Dec 2, 2021
Grant date	—

Abstract

A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.

First claim

1 . A semiconductor device, comprising:
a gate structure disposed over a channel region; and a source/drain region, wherein: the gate structure includes:
a gate dielectric layer over the channel region;
one or more work function adjustment material layers over the gate dielectric layer; and
a metal gate electrode layer over the one or more work function adjustment material layers,
the one or more work function adjustment material layers includes an aluminum containing layer, the aluminum containing layer is a TiAl layer or a TiAlC layer, a diffusion barrier layer containing Al and Ti is disposed at at least one of a bottom portion or a top portion of the aluminum containing layer, and the diffusion barrier layer is a Ti-rich layer having a higher Ti concentration than a center of the aluminum containing layer.

2 - 3 . (canceled)

4 . The semiconductor device of claim 1 , wherein:
a Ti concentration of the diffusion barrier layer is in a range from 20 atomic % to 50 atomic %, and a Ti concentration of the center portion is in a range from 5 atomic % to 15 atomic %.

5 . The semiconductor device of claim 1 , wherein a Ti, Ta or Si concentration in the diffusion barrier layer gradually increases from a side on the center portion to a surface of the aluminum containing layer.

6 . The semiconductor device of claim 1 , wherein a Ti concentration in the diffusion barrier layer is constant.

7 . The semiconductor device of claim 1 , wherein a Ti concentration in the center portion is constant.

8 . The semiconductor device of claim 1 , wherein an aluminum concentration of the aluminum containing layer is in a range from 10 atomic % to 30 atomic %.

9 . The semiconductor device of claim 1 , wherein a thickness of the center portion is in a range from 20% to 60% of a total thickness of the aluminum containing layer.

10 . The semiconductor device of claim 1 , wherein the one or more work function adjustment material layers includes at least one of WCN, WN, W, Ru, or TiNC or TiSiN disposed between the aluminum containing layer and the gate dielectric layer.

11 . A complementary metal oxide semiconductor (CMOS) device, comprising:
a first field effect transistor (FET) including a first gate structure disposed over a first channel region; and a second FET including a second gate structure disposed over a second channel region, wherein: the first FET is an n-type FET, and second FET is a p-type FET, and the first gate structure includes:
a gate dielectric layer;
a first work function adjustment material layer over the gate dielectric layer; and
a metal gate electrode layer over the first work function adjustment material layer, the second gate structure includes:
a gate dielectric layer;
a second work function adjustment material layer over the gate dielectric layer;
the first work function adjustment material layer over the second work function adjustment material layer; and
the metal gate electrode layer over the first work function adjustment material layer,
the metal gate electrode and the first work function adjustment material layer are continuous between the first FET and the second FET, such that the metal gate electrode is disposed over the gate dielectric layer of the first FET, over the second work function adjustment material layer of the second FET and over a sidewall of the second work function adjustment material layer at a boundary of the first FET and the second FET, the first work function adjustment material layer includes TiAl or TiAlC, the first work function adjustment material layer includes a diffusion barrier layer containing Al and Ti at at least one of a bottom portion or a top portion of the first work function adjustment material layer, and the diffusion barrier layer is a Ti-rich layer having a higher Ti concentration than a center of the first work function adjustment material layer.

12 . The CMOS device of claim 11 , wherein the second work function adjustment material layer includes at least one of WN, WCN, W, or Ru.

13 . The CMOS device of claim 11 , wherein:
the second work function adjustment material layer includes at least one of WN, WCN, W, Ru, TiN and TiSiN, and at least one of the one or more layers is discontinuous between the first FET and the second FET.

14 . The CMOS device of claim 13 , wherein the first work function adjustment material layer covers a top face and side face of the at least one of the one or more layers at a metal boundary of the first FET and the second FET.

15 . The CMOS device of claim 11 , wherein the diffusion barrier layer is disposed at the bottom portion of the first work function adjustment material layer.

16 . The CMOS device of claim 11 , wherein the second work function adjustment material layer in second FET does not contain Al.

17 . The CMOS device of claim 11 , wherein:
a Ti concentration of the Ti-rich layer is in a range from 20 atomic % to 50 atomic %, and a Ti concentration of the center portion is in a range from 5 atomic % to 15 atomic %.

18 . The CMOS device of claim 11 , wherein the first work function adjustment material layer is disposed directly on the gate dielectric layer.

19 . The CMOS device of claim 11 , wherein a thickness of the center portion is in a range from 20% to 90% of a total thickness of the aluminum containing layer.

20 . (canceled)

21 . A semiconductor device, comprising:
a gate structure disposed over a channel region; and a source/drain region, wherein: the gate structure includes:
a gate dielectric layer over the channel region;
one or more work function adjustment material layers over the gate dielectric layer; and
a metal gate electrode layer over the one or more work function adjustment material layers,
the one or more work function adjustment material layers includes an aluminum containing layer containing Al and Ti, a diffusion barrier layer containing Al and Ti is disposed at a bottom portion of the aluminum containing layer, and the diffusion barrier layer has a higher Ti concentration than a center of the aluminum containing layer.

22 . The semiconductor device of claim 21 , wherein an Al/Ti ratio of the diffusion barrier layer is in a range from 0.2 to 1.2.

23 . The semiconductor device of claim 21 , wherein a Ti concentration of the diffusion barrier layer is in a range from 30 atomic % to 40 atomic %.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• More Shahaji B
• Savant Chandrashekhar Prakash
• Yu Tien-Wei
• Tsai Chia-Ming

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title