Integrated Assemblies Comprising Hydrogen Diffused Within Two or More Different Semiconductor Materials, and Methods of Forming Integrated Assemblies

Patent metadata

Field	Value
Publication number	US-2021375868-A1
Application number	US-202117396049-A
Country	US
Kind code	A1
Filing date	Aug 6, 2021
Priority date	Mar 11, 2019
Publication date	Dec 2, 2021
Grant date	—

Abstract

Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

First claim

1 - 23 . (canceled)

24 . A method of forming an integrated assembly, comprising:
forming a construction which includes a first semiconductor region between a pair of second semiconductor regions; the first semiconductor region comprising a different composition relative to the second semiconductor regions; forming a transistor gate adjacent the first semiconductor region; diffusing hydrogen within the first and second semiconductor regions; the conductivity of the second semiconductor regions increasing in response to the hydrogen diffused therein to convert the second semiconductor regions to source/drain regions; the first semiconductor region having the hydrogen diffused therein being a channel region between the source/drain regions; and the source/drain regions, the channel region and the transistor gate being together comprised by a transistor; the transistor gate being configured to induce an electric field in the channel region in an ON-state of the transistor and thereby couple the source/drain regions with one another through the channel region in the ON-state; the transistor having an OFF-state; the channel region having a lower conductivity than the source/drain regions in the OFF-state of the transistor.

25 . The method of claim 24 wherein the second semiconductor regions of said pair are a same composition as one another.

26 . The method of claim 24 wherein the second semiconductor regions of said pair are different compositions relative to one another.

27 . The method of claim 24 wherein the conductivity of the source/drain regions is at least about 10-times greater than the conductivity of the channel region in the OFF-state of the transistor.

28 . The method of claim 24 wherein the conductivity of the source/drain regions is at least about 100-times greater than the conductivity of the channel region in the OFF-state of the transistor.

29 . The method of claim 24 wherein the conductivity of the source/drain regions is at least about 1000-times greater than the conductivity of the channel region in the OFF-state of the transistor.

30 . The method of claim 24 wherein the transistor gate is formed prior to the diffusing of the hydrogen.

31 . The method of claim 24 wherein the first and second semiconductor regions comprise first and second semiconductor materials, respectively; and wherein the first and second semiconductor materials comprise at least one metal in combination with one or more of oxygen, sulfur, selenium and tellurium.

32 . The method of claim 31 wherein the at least one metal is one or more of aluminum, gallium, indium, thallium, tin, cadmium and zinc.

33 . The method of claim 31 wherein the first semiconductor material comprises GaO, and wherein the second semiconductor material comprises InGaZnO; where the chemical formulas indicate primary constituents rather than a specific stoichiometry.

34 . The method of claim 24 comprising:
coupling one of the source/drain regions with a storage element;
coupling the other of the source/drain regions with a digit line;
coupling the transistor gate with a wordline; and
wherein the transistor and the storage element are comprised by a memory cell.

35 . The method of claim 34 wherein the memory cell is one of many substantially identical memory cells formed within a memory array; wherein the wordline is one of many wordlines formed within the memory array; wherein the digit line is one of many digit lines formed within the memory array; and wherein each of the memory cells is uniquely addressed through one of the digit lines in combination with one of the wordlines.

36 . The method of claim 35 wherein the memory array is formed proximate circuitry having interfaces between silicon and silicon dioxide; and wherein the diffusing of the hydrogen also diffuses the hydrogen into the circuitry to passivate said interfaces.

37 . The method of claim 35 wherein the memory array is formed over CMOS circuitry, with the CMOS circuitry including interfaces between silicon and silicon dioxide; and wherein the diffusing of the hydrogen also diffuses the hydrogen into the CMOS circuitry to passivate said interfaces.

38 . The method of claim 35 wherein the memory array is formed within a tier; and wherein the tier is within a vertically-stacked arrangement of tiers and is over at least one other of the tiers within the vertically-stacked arrangement.

Assignees

• Micron Technology Inc

Inventors

• Karda Kamal M
• Lee Yi Fang
• Liu Haitao
• Ramaswamy Durai Vishak Nirmal
• Gandhi Ramanathan
• Sarpatwari Karthik
• Sills Scott E
• Chhajed Sameer

Classifications

• H10P32/171

  being group IV material · CPC title

• H10P32/12 Primary

  between a solid phase and a gaseous phase · CPC title

• H10B12/00

  Dynamic random access memory [DRAM] devices · CPC title

• H10D99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title