Electronic device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2021351491-A1
Application number	US-202117383403-A
Country	US
Kind code	A1
Filing date	Jul 22, 2021
Priority date	Jul 31, 2018
Publication date	Nov 11, 2021
Grant date	—

Abstract

A method of manufacturing an electronic device includes providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer, and removing at least a portion of each of the two conductive layers to respectively form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.

First claim

What is claimed is:

1 . A method of manufacturing an electronic device, comprising:
providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer; and removing at least a portion of each of the two conductive layers to respectively form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.

2 . The method of claim 1 , wherein after providing the core dielectric layer with the two conductive layers,
forming a patterned mask to cover one of the two conductive layers, and removing a portion of the one of the two conductive layers exposed by the patterned mask to form the antenna pattern with an undercut.

3 . The method of claim 1 , wherein after providing the core dielectric layer with the two conductive layers,
forming a patterned dielectric layer on one of the two conductive layers, wherein the patterned dielectric layer exposes a portion of the one of the two conductive layers, and removing the portion of the one of the two conductive layers to form the circuit pattern of the chip package, wherein the circuit pattern comprising a slanted sidewall connected to the patterned dielectric layer and the core dielectric layer.

4 . The method of claim 3 , wherein after forming the circuit pattern,
disposing a semiconductor chip with an attaching layer on the patterned dielectric layer opposite to the circuit pattern, wherein a portion of the attaching layer extends to pass through the patterned dielectric layer and the circuit pattern to be in contact with the core dielectric layer.

5 . The method of claim 1 , wherein removing at least the portion of each of the two conductive layers comprises:
removing one of the two conductive layers to expose a surface of the core dielectric layer, and printing a conductive paste on the surface of the core dielectric layer to form the antenna pattern.

6 . The method of claim 1 , further comprising:
thinning one of the two conductive layers before removing at least the portion of each of the two conductive layers.

7 . The method of claim 6 , wherein forming the antenna pattern comprises:
forming a conductive material to cover a portion of the one of the two conductive layers after the thinning, and removing a remaining portion of the one of the two conductive layers exposed by the conductive material to form the antenna pattern.

8 . The method of claim 1 , further comprising:
providing an alignment mark on the core dielectric layer before removing at least a portion of each of the two conductive layers, wherein after one of the antenna pattern and the circuit pattern is formed, the alignment mark is employed to remove at least a portion of the other one of the two conductive layers with respect to the core dielectric layer.

9 . A method of manufacturing an electronic device, comprising:
forming a composite structure, wherein the composite structure comprises:
a core dielectric layer comprising a first surface, a second surface opposite to the first surface, and an alignment mark;
a first conductive layer formed on the first surface of the core dielectric layer; and
a second conductive layer formed on the second surface of the core dielectric layer;
patterning the first conductive layer and the second conductive layer to respectively form an antenna pattern and a circuit pattern through the alignment mark; encapsulating the antenna pattern to form an antenna package; encapsulating a plurality of semiconductor chips disposed on the circuit pattern to form a chip package, wherein the semiconductor chips are electrically coupled to the circuit pattern and the antenna pattern; and cutting the antenna package, the chip package, and the core dielectric layer disposed therebetween into a plurality of electronic devices.

10 . The method of claim 9 , wherein patterning the first conductive layer comprises:
forming a patterned mask on the first conductive layer, wherein the patterned mask exposes a portion of the first conductive layer, and removing the portion of the first conductive layer to form the antenna pattern with a first undercut.

11 . The method of claim 10 , wherein forming the antenna pattern with the first undercut comprises:
performing a wet etching process which is selective to a material of the first conductive layer.

12 . The method of claim 9 , wherein patterning the second conductive layer comprises:
forming a patterned dielectric layer on the second conductive layer, wherein the patterned dielectric layer exposes a portion of the second conductive layer, and removing the portion of the second conductive layer to form the circuit pattern with a second undercut.

13 . The method of claim 12 , wherein forming the circuit pattern with the second undercut comprises:
performing a wet etching process which is selective to a material of the second conductive layer.

14 . The method of claim 9 , wherein patterning the second conductive layer comprises:
thinning the second conductive layer to form a thinned conductive layer; and removing a portion of the thinned conductive layer to form the circuit pattern.

15 . The method of claim 9 , wherein forming the chip package comprises:
attaching a back surface of each of the plurality of semiconductor chips to the core dielectric layer by forming an attaching layer between the back surface and the core dielectric layer, wherein during the attaching, the attaching layer fills a spacing of the circuit pattern to be in contact with the core dielectric layer.

16 . The method of claim 9 , wherein forming the chip package comprises:
attaching a conductive element to the circuit pattern through a conductive joint, wherein the conductive element is a T-shaped post.

17 . A method of manufacturing an electronic device, comprising:
forming a chip package on a core dielectric layer, wherein:
the chip package comprises a semiconductor chip, an insulating encapsulation encapsulating the semiconductor chip, and a redistribution structure electrically coupled to the semiconductor chip, and
the redistribution structure comprises a circuit pattern and a patterned dielectric layer, wherein the circuit pattern is formed at an outermost side of the chip package and directly formed on the core dielectric layer, and the patterned dielectric layer is formed on the circuit pattern and covered by the insulating encapsulation; and
forming an antenna package on the core dielectric layer, wherein the antenna package and the chip package are formed at two opposing sides of the core dielectric layer, and the antenna package is electrically coupled to the chip package.

18 . The method of claim 17 , wherein before forming the chip package and the antenna package, the method further comprises:
providing the core dielectric layer with two conductive layers formed on the two opposing sides; and patterning each of the two conductive layers to respectively form an antenna pattern of the antenna package and the circuit pattern of the chip package.

19 . The method of claim 18 , wherein:
forming a patterned mask to cover one of the two conductive layers before the removing, and removing a portion of the one of the two conductive layers exposed by the patterned mask to form the antenna pattern with an undercut.

20 . The method of claim 18 , wherein forming the circuit pattern comprises:
thinning one of the two conductive layers to form a thinned conductive lay

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Pei-Hsuan
• Hsieh Ching-Hua
• Hwang Chien-Ling
• Chiu Yu-Ting
• Kuo Jui-Chang

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title