Phase shift mask, array substrate, fabrication method thereof and display apparatus

US2021333704A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2021333704-A1
Application numberUS-201816346192-A
CountryUS
Kind codeA1
Filing dateNov 1, 2018
Priority dateFeb 11, 2018
Publication dateOct 28, 2021
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel includes a method of fabricating an array substrate. The method includes forming a metal layer (1) on a substrate, and patterning the metal layer (1) using a phase shift mask to form a pattern of metal wiring. The phase shift mask includes a substrate and a wiring light shielding portion (02) on the substrate (01). The wiring light shielding portion (02) includes a light shielding region (021) and a phase shift region (022). In a direction perpendicular to the extending direction of the wiring light shielding portion (02) a width of the light shielding region (021) is larger than a width of the pattern of the metal wiring formed by the wiring light shielding portion (02).

First claim

Opening claim text (preview).

1 . A method of fabricating an array substrate, comprising: forming a metal layer on a substrate; and patterning the metal layer using a phase shift mask to form a pattern of metal wiring, wherein the phase shift mask comprises a substrate and a wiring light shielding portion on the substrate; the wiring light shielding portion comprises a light shielding region and a phase shifting region, and in a direction perpendicular to an extension direction of the wiring light shielding portion, a width of the light shielding region is larger than a width of the pattern of the metal wiring formed by the wiring light shielding portion. 2 . The fabrication method according to claim 1 , before the metal layer is formed on the substrate, further comprising: forming a pattern of a gate electrode on the substrate; forming a gate insulating layer covering the pattern of the gate electrode; and forming a pattern of a semiconductor layer on the gate insulating layer. 3 . The fabrication method according to claim 1 , wherein the phase shift mask further comprises a channel light transmitting portion and two electrode light shielding portions on both opposite sides of the channel light transmitting portion, and patterning the metal layer using the phase shift mask further comprises: forming a pattern of a drain electrode and a pattern of a source electrode by the electrode light shielding portions, and a channel between the pattern of the drain electrode and the pattern of the source electrode. 4 . The fabrication method according to claim 3 , wherein a difference between the width of the light shielding region and the width of the pattern of the metal wiring is a compensation width, and the compensation width is negatively correlated to a width of the channel light transmitting portion. 5 . The fabrication method according to claim 4 , wherein the compensation width and the width of the channel light transmitting portion meets the following relationship: wherein y represents the compensation width, x represents the width of the channel light transmission portion, and K and b are constants. 6 . The fabrication method according to claim 4 , wherein the compensation width and the width of the channel light transmitting portion meet the following relationship: wherein y represents the compensation width, x represents the width of the channel light transmitting portions, and ΔT represents a difference between a thickness of photoresist in a region of the channel light transmitting portion and a thickness of photoresist in a region of the wiring light shielding portion. 7 . The fabrication method according to claim 5 , wherein K is approximately equal to 1.17 and b is approximately equal to 3.52. 8 . The fabrication method according to claim 1 , wherein the wiring light shielding portion comprises a light shielding layer and a phase shifting layer, the light shielding layer covers the light shielding region, and the phase shifting layer covers at least the phase shifting region. 9 . The fabrication method according to claim 8 , wherein the phase shifting layer covers both the light shielding region and the phase shifting region. 10 . The fabrication method according to claim 9 , wherein a shape of the wiring light shielding portion is a strip. 11 . The fabrication method according to claim 8 , wherein the light shielding layer is made of chromium. 12 . The fabrication method according to claim 8 , wherein the phase shifting layer is made of a phase shifting material, wherein the phase shifting material is configured to enable light to generate phase change of 180 degrees. 13 . An array substrate fabricated by the method according to claim 1 . 14 . A display apparatus comprising the array substrate according to claim 13 . 15 . A phase shift mask, comprising: a substrate; and a wiring light shielding portion n the substrate; wherein the wiring light shielding portion comprises a light shielding region and a phase shifting region, and in a direction perpendicular to an extension direction of the wiring light shielding portion, a width of the light shielding region is larger than a width of a pattern formed by the wiring light shielding portion. 16 . The phase shift mask according to claim 15 , further comprising: a channel light transmitting portion; and two electrode light shielding portions respectively on both opposite sides of the channel light transmitting portion; wherein a difference between the width of the light shielding region and the width of the pattern is a compensation width, and the compensation width is negatively correlated to a width of the channel light transmitting portion. 17 . The phase shift mask according to claim 16 , wherein the compensation width and the width of the channel light transmitting portion meets the following relationship: wherein, y represents the compensation width, x represents the width of the channel light transmission portion, and K and b are constants. 18 . The phase shift mask according to claim 16 , wherein the compensation width and the width of the channel light transmitting portion meet the following relationship: wherein y represents the compensation width, and x represents the width of the channel light transmitting portions, the ΔT represents a difference between a thickness of photoresist in a corresponding region of the channel light transmitting portion and a thickness of photoresist in a corresponding region of the wiring light shielding portion during exposure. 19 . (canceled) 20 . The phase shift mask according to claim 15 , wherein the wiring light shielding portion comprises a light shielding layer and a phase shifting layer; wherein the light shielding layer covers the light shielding region, and the phase shifting layer covers at least the phase shifting region. 21 . The phase shift mask according to claim 20 , wherein the phase shifting layer covers both the light shielding region and the phase shifting region

Assignees

Inventors

Classifications

  • using masks, e.g. half-tone masks · CPC title

  • of thin-film transistors [TFT] · CPC title

  • G03F1/26Primary

    Phase shift masks [PSM]; PSM blanks; Preparation thereof · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US2021333704A1 cover?
A display panel includes a method of fabricating an array substrate. The method includes forming a metal layer (1) on a substrate, and patterning the metal layer (1) using a phase shift mask to form a pattern of metal wiring. The phase shift mask includes a substrate and a wiring light shielding portion (02) on the substrate (01). The wiring light shielding portion (02) includes a light shieldi…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Beijing Boe Display Tech Co
What technology area does this patent fall under?
Primary CPC classification G03F1/26. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Oct 28 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).