Integrated circuit and method capable of minimizing circuit area of non-volatile memory circuit
US-2023059746-A1 · Feb 23, 2023 · US
US2021320792A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2021320792-A1 |
| Application number | US-201917271700-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 25, 2019 |
| Priority date | Aug 28, 2018 |
| Publication date | Oct 14, 2021 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A method for storing key data in an electronic component formed as an integrated programmable circuit, such as a field programmable gate array, which includes a base structure consisting of base elements, wherein configuration data is loaded, for each current program, onto the base elements and stored in a volatile matter, the key data is divided into key sub-data blocks, and a base element position is selected for each key sub-data block, where upon generating the configuration data for each current program or circuit function of the electronic component, selected base element positions of the key sub-data blocks are considered, while loading the configuration data, key sub-data blocks are stored in the base elements defined by selected base element positions, and after successfully programming the electronic component, the key sub-data blocks of base elements specified by selected base element positions are ascertained and assembled to form the key data.
Opening claim text (preview).
1 .- 9 . (canceled) 10 . A method for storing key data in an electronic component comprising a programmable integrated circuit, said electronic component having a basic structure consisting of base elements, wherein configuration data for a respective current programming of the electronic component being loaded into the respective base elements and being stored in volatile fashion, the method comprising: dividing the key data into key data subblocks; and selecting a base element position in the basic structure of the electronic component for each key data subblock, the base element positions selected for the respective key data subblocks being filed in a lockout data element; wherein creation of the configuration data for the respective current programming of the electronic component takes into consideration the base element positions selected for the key data subblocks such that the selected base element positions from the lockout data element are incorporated into the configuration data of the respective current programming via a constraint file; wherein the loading of the configuration data for the respective current programming into the electronic component comprising filing the key data subblocks in those base elements which are stipulated by the selected base element positions filed in the lockout data element; and wherein after the electronic component has been programmed the key data subblocks are ascertained from the respective base elements stipulated by the selected base element positions and are assembled to form the key data. 11 . The method as claimed in claim 10 , wherein the lockout data element is filed in a permanent memory in encrypted form 12 . The method as claimed in claim 10 , wherein the key data are divided into key data subblocks such that the respective key data subblock is fileable in precisely one base element of the basic structure. 13 . The method as claimed in claim 11 , wherein the key data are divided into key data subblocks such that the respective key data subblock is fileable in precisely one base element of the basic structure. 14 . The method as claimed in claim 10 , wherein a selection regarding the base element positions for the key data subblocks is made in accordance with a random principle. 15 . The method as claimed in claim 10 , wherein a base element of the basic structure of the electronic component is formed via a lookup-table (LUT) unit and an assigned dynamic configuration cell. 16 . The method as claimed in claim 15 , wherein the configuration cell of the base element is formed as static RAM. 17 . The method as claimed in claim 1 , wherein the key data subblocks are read from the respective base elements by a control unit via a configuration interface of the electronic component utilizing information about the selected base element positions and are assembled to form the key data. 18 . The method as claimed in claim 10 , wherein the key data subblocks are read from the respective base elements aided by a separate application and are assembled to form the key data (K); and wherein the application utilizing information about the selected base element positions. 19 . The method as claimed in claim 10 , wherein the programmable integrated circuit comprises a field programmable gate array (FPGA).
in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title
Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage · CPC title
Details relating to cryptographic hardware or logic circuitry · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.