Three-dimensional memory device and method for forming the same

Patent metadata

Field	Value
Publication number	US-2021305277-A1
Application number	US-202117329103-A
Country	US
Kind code	A1
Filing date	May 24, 2021
Priority date	Mar 31, 2020
Publication date	Sep 30, 2021
Grant date	—

Abstract

In certain aspects, a first opening extending vertically through a first dielectric deck including a first plurality of interleaved sacrificial layers and dielectric layers above a substrate is formed. A high-k dielectric layer and a channel sacrificial layer free of polysilicon are subsequently formed along a sidewall of the first opening. A second opening extending vertically through a second dielectric deck including a second plurality of interleaved sacrificial layers and dielectric layers on the first dielectric deck is formed to expose the channel sacrificial layer in the first opening. The channel sacrificial layer is removed in the first opening. A memory film and a semiconductor channel are subsequently formed over the high-k dielectric layer along sidewalls of the first and second openings.

First claim

What is claimed is:

1 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a first opening extending vertically through a first dielectric deck comprising a first plurality of interleaved sacrificial layers and dielectric layers above a substrate; subsequently forming a high dielectric constant (high-k) dielectric layer and a channel sacrificial layer free of polysilicon along a sidewall of the first opening; forming a second opening extending vertically through a second dielectric deck comprising a second plurality of interleaved sacrificial layers and dielectric layers on the first dielectric deck to expose the channel sacrificial layer in the first opening; removing the channel sacrificial layer in the first opening; and subsequently forming a memory film and a semiconductor channel over the high-k dielectric layer along sidewalls of the first and second openings.

2 . The method of claim 1 , wherein the high-k dielectric layer comprises aluminum oxide, and the channel sacrificial layer comprises silicon oxide.

3 . The method of claim 1 , further comprising prior to subsequently forming the high-k dielectric layer and the channel sacrificial layer, forming a semiconductor plug at a bottom of the first opening.

4 . The method of claim 1 , further comprising after subsequently forming the memory film and the semiconductor channel, replacing the sacrificial layers in the first and second dielectric decks with a plurality of conductive layers.

5 . The method of claim 4 , wherein replacing comprises:
removing the sacrificial layers to leave a plurality of lateral recesses between the dielectric layers in the first and second dielectric decks; depositing a plurality of adhesive layers over the dielectric layers in the lateral recesses; and depositing a plurality of gate electrodes over the adhesive layers in the lateral recesses.

6 . The method of claim 5 , wherein the high-k dielectric layer does not extend between each of the adhesive layers and the adjacent dielectric layer.

7 . The method of claim 1 , wherein subsequently forming the high-k dielectric layer and the channel sacrificial layer comprises:
depositing the high-k dielectric layer along the sidewall of the first opening; depositing the channel sacrificial layer over the high-k dielectric layer in the first opening; and planarizing top surfaces of the high-k dielectric layer and the channel sacrificial layer to be flush with a top surface of the first dielectric deck.

8 . The method of claim 1 , further comprising prior to removing the channel sacrificial layer, forming another high-k dielectric layer along the sidewall of the second opening, such that the memory film is formed over the high-k dielectric layer and the another high-k dielectric layer in the first and second openings, respectively.

9 . The method of claim 1 , wherein subsequently forming the memory film and the semiconductor channel comprises subsequently depositing a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and a polysilicon layer along the sidewalls of the first and second openings in this order.

10 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a first opening extending vertically through a first dielectric deck comprising a first plurality of interleaved sacrificial layers and dielectric layers above a substrate; forming a channel sacrificial layer comprising a material other than polysilicon along a sidewall of the first opening; forming a second opening extending vertically through a second dielectric deck comprising a second plurality of interleaved sacrificial layers and dielectric layers on the first dielectric deck to expose the channel sacrificial layer in the first opening; removing the channel sacrificial layer in the first opening; and subsequently forming a memory film and a semiconductor channel along sidewalls of the first and second openings.

11 . The method of claim 10 , wherein the material in the channel sacrificial layer comprises ceramic.

12 . The method of claim 10 , wherein the material in the channel sacrificial layer comprises a dopant into polysilicon.

13 . The method of claim 10 , further comprising prior to forming the channel sacrificial layer, forming a semiconductor plug at a bottom of the first opening.

14 . The method of claim 10 , further comprising after subsequently forming the memory film and the semiconductor channel, replacing the sacrificial layers in the first and second dielectric decks with a plurality of conductive layers.

15 . The method of claim 10 , wherein subsequently forming the memory film and the semiconductor channel comprises subsequently depositing a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and a polysilicon layer along the sidewalls of the first and second openings in this order.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Peng Shuangshuang
• Geng Jingjing
• Wu Jiajia
• Li Tuo

Classifications

• H10D64/01352

  with sacrificial oxide · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/68

  Organic materials, e.g. photoresists · CPC title

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H01L27/1157

  Electricity · mapped topic