Memory device

Patent metadata

Field	Value
Publication number	US-2021287733-A1
Application number	US-202017015408-A
Country	US
Kind code	A1
Filing date	Sep 9, 2020
Priority date	Mar 10, 2020
Publication date	Sep 16, 2021
Grant date	—

Abstract

According to one embodiment, a driver that sequentially supplies a first voltage, a second voltage higher than the first voltage, and the first voltage to the bit line, during the writing operation to the first memory cell. The driver supplies a third voltage to the second word line and a fourth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if a data is a first data. The driver supplies a fifth voltage to the second word line and a sixth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if the data is a second data. At least the sixth voltage is larger than the fourth voltage or the fifth voltage is larger than the third voltage.

First claim

What is claimed is:

1 . A memory device comprising:
a semiconductor substrate having a main surface, the main surface extending in a first direction and a second direction intersecting the first direction; a first memory pillar including;
a first variable resistance memory layer extending in a third direction intersecting the first direction and the second direction;
a first semiconductor layer extending in the third direction, the first semiconductor layer contacting with the first variable resistance memory layer; and
a first insulating layer extending in the third direction, the first insulating layer contacting with the first semiconductor layer;
a second memory pillar including;
a second variable resistance memory layer extending in the third direction;
a second semiconductor layer extending in the third direction, the second semiconductor layer contacting with the second variable resistance memory layer; and
a second insulating layer extending in the third direction, the second insulating layer contacting with the second semiconductor layer;
a bit line extending in the first direction, the bit line connecting to one end of the first memory pillar and one end of the second memory pillar; a first selecting gate line extending in the second direction, the first selecting gate line forming a first selecting transistor by being opposite to the first semiconductor layer through the first insulating layer; a first word line extending in the second direction, the first word line forming a first memory cell by being opposite to the first variable resistance memory layer through the first semiconductor layer and the first insulating layer; a second selecting gate line arranged at a same position as the first selecting gate line in the third direction, the second selecting gate line extending in the second direction, the second selecting gate line forming a second selecting transistor by being opposite to the second semiconductor layer through the second insulating layer; a second word line arranged at a same position as the first word line in the third direction, the second word line extending in the second direction, the second word line forming a second memory cell by being opposite to the second variable resistance memory layer through the second semiconductor layer and the second insulating layer; and a driver configured to supply voltages to each of the bit line, the first selecting gate line, the second selecting gate line, and the second word line at a writing operation; wherein the driver sequentially supplies a first voltage, a second voltage higher than the first voltage, and the first voltage to the bit line, during the writing operation to the first memory cell; the driver supplies a third voltage to the second word line and a fourth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if a data written in the first memory cell is a first data; the driver supplies a fifth voltage to the second word line and a sixth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if the data written in the first memory cell is a second data different from the first data; and at least the sixth voltage is larger than the fourth voltage or the fifth voltage is larger than the third voltage.

2 . The memory device according to claim 1 , wherein the fifth voltage is a voltage configured to turn on the second memory cell, and the sixth voltage is a voltage configured to turn on the second selecting transistor.

3 . The memory device according to claim 1 , further comprising:
a source line extending in the first direction, the source line connecting with another end of the first memory pillar and another end of the second memory pillar, wherein the bit line and the source line are conducted by the second memory pillar while changing the voltage of the bit line from the second voltage to the first voltage if the data written in the first memory cell is the second data.

4 . The memory device according to claim 1 , wherein
the first semiconductor layer and the first insulating layer are arranged from another end to the one end of the first memory pillar; the first variable resistance memory layer is arranged from the other end to a first point of the first memory pillar; and a position of the first point in the third direction is lower than a position of the first selecting gate line in the third direction and higher than a position of the first word line in the third direction; the second semiconductor layer and the second insulating material layer are arranged from another end to the one end of the second memory pillar; the second variable resistance memory layer is arranged from the other end to a second point of the second memory pillar; and a position of the second point in the third direction is lower than a position of the second selecting gate line in the third direction and higher than a position of the second word line in the third direction.

5 . The memory device according to claim 1 , wherein the second selecting gate line is connected to a common second selecting gate line.

6 . The memory device according to claim 5 , wherein a resistance of the common second selecting gate line is lower than a resistance of the second selecting gate line.

7 . The memory device according to claim 1 , wherein a voltage of the bit line is controlled to gently fall while changing from the second voltage to the first voltage if the data written in the first memory cell is the first data.

8 . A memory device comprising:
A semiconductor substrate having a main surface, the main surface extending in a first direction and a second direction intersecting the first direction; a first memory pillar including:
a first variable resistance memory layer extending in a third direction intersecting the first direction and the second direction;
a first semiconductor layer extending in the third direction, the first semiconductor layer contacting with the first variable resistance memory layer; and
a first insulating layer extending in the third direction, the first insulating layer contacting with the first semiconductor layer;
a bit line extending in the first direction, the bit line connecting to one end of the first memory pillar; a first selecting gate line extending in the second direction, the first selecting gate line forming a first selecting transistor by being opposite to the first semiconductor layer through the first insulating layer; a first word line extending in the second direction, the first word line forming a first memory cell by being opposite to the first variable resistance memory layer through the first semiconductor layer and the first insulating material layer; a second selecting gate line arranged at a lower position than the first word line in the third direction, the second selecting gate line extending in the second direction, the second selecting gate line forming a second selecting transistor by being opposite to the first semiconductor layer through the first insulating layer; and a driver configured to supply voltages to each of the bit line, the second selecting gate line, and the first word line at a writing operation; wherein the driver sequentially supplies a first voltage, a second voltage higher than the first voltage, and the first voltage to the bit line, during the writing operation to the first memory cell; the driver supplies a seventh voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if a data written in the first memory cell is a first data; the driver su

Assignees

• Kioxia Corp

Inventors

• Iizuka Takahiko
• Takashima Daisaburo
• Ogiwara Ryu

Classifications

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title