Mixing circuit with high harmonic suppression ratio

US2021281218A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2021281218-A1
Application numberUS-202017037692-A
CountryUS
Kind codeA1
Filing dateSep 30, 2020
Priority dateMar 3, 2020
Publication dateSep 9, 2021
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides a mixing circuit with high harmonic suppression ratio, including: a multi-phase generation module, which receives a first input signal and generates eight first square wave signals with a phase difference of 45°; a quadrature phase generation module, which receives a second input signal and generates four second square wave signals with a phase difference of 90°; a harmonic suppression module, connected with an output end of the quadrature phase generation module to filter out higher order harmonic components in the second square wave signals; and a mixing module, connected with output ends of the multi-phase generation module and the harmonic suppression module to mix output signals of the multi-phase generation module and the harmonic suppression module. The mixing circuit with high harmonic suppression ratio adds a harmonic suppression module on the basis of multi-phase mixing, thereby improving the harmonic suppression ratio of the output signal.

First claim

Opening claim text (preview).

We claim: 1 . A mixing circuit with high harmonic suppression ratio, at least comprising: a multi-phase generation module, which receives a first input signal and generates eight first square wave signals with a phase difference of 45°; a quadrature phase generation module, which receives a second input signal and generates four second square wave signals with a phase difference of 90°; a harmonic suppression module, connected with an output end of the quadrature phase generation module to filter out higher order harmonic components in the second square wave signals; and a mixing module, connected with output ends of the multi-phase generation module and the harmonic suppression module to mix output signals of the multi-phase generation module and the harmonic suppression module. 2 . The mixing circuit with high harmonic suppression ratio according to claim 1 , wherein the first square wave signals are same frequency signals or frequency division signals of the first input signal. 3 . The mixing circuit with high harmonic suppression ratio according to claim 1 , wherein the multi-phase generation module comprises: a first limiting amplifier unit, which receives the first input signal and amplifies the first input signal into a rail-to-rail signal; and a first frequency division unit, connected with an output end of the first limiting amplifier unit, and dividing a frequency of an output signal of the first limiting amplifier unit. 4 . The mixing circuit with high harmonic suppression ratio according to claim 1 , wherein the first input signal is a pair of differential signals. 5 . The mixing circuit with high harmonic suppression ratio according to claim 2 , wherein the first input signal is a pair of differential signals. 6 . The mixing circuit with high harmonic suppression ratio according to claim 3 , wherein the first input signal is a pair of differential signals. 7 . The mixing circuit with high harmonic suppression ratio according to claim 1 , wherein the second square wave signals are same frequency signals or frequency division signals of the second input signal. 8 . The mixing circuit with high harmonic suppression ratio according to claim 1 , wherein the quadrature phase generation module comprises: a second limiting amplifier unit, which receives the second input signal and amplifies the second input signal into a rail-to-rail signal; and a second frequency division unit, connected with an output end of the second limiting amplifier unit, and dividing a frequency of an output signal of the second limiting amplifier unit. 9 . The mixing circuit with high harmonic suppression ratio according to claim 1 , wherein the second input signal is a pair of differential signals. 10 . The mixing circuit with high harmonic suppression ratio according to claim 7 , wherein the second input signal is a pair of differential signals. 11 . The mixing circuit with high harmonic suppression ratio according to claim 8 , wherein the second input signal is a pair of differential signals. 12 . The mixing circuit with high harmonic suppression ratio according to claim 1 , wherein the harmonic suppression module comprises a low-pass filter unit. 13 . The mixing circuit with high harmonic suppression ratio according to claim 1 , wherein the mixing module comprises a Gilbert mixing unit. 14 . The mixing circuit with high harmonic suppression ratio according to claim 13 , wherein the Gilbert mixing unit comprises three subunits with a tail current ratio of 1:√{square root over (2)}:1.

Assignees

Inventors

Classifications

  • comprising components for selecting a particular frequency component of the output · CPC title

  • Double balanced arrangements, i.e. where both input signals are differential · CPC title

  • H03D7/1441Primary

    using field-effect transistors (H03D7/145 takes precedence) · CPC title

  • at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002) · CPC title

  • H03D7/1425Primary

    with transistors · CPC title

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What does patent US2021281218A1 cover?
The present disclosure provides a mixing circuit with high harmonic suppression ratio, including: a multi-phase generation module, which receives a first input signal and generates eight first square wave signals with a phase difference of 45°; a quadrature phase generation module, which receives a second input signal and generates four second square wave signals with a phase difference of 90°;…
Who is the assignee on this patent?
Verisilicon Microelectronics Shanghai Co Ltd, Verisilicon Holdings Co Ltd
What technology area does this patent fall under?
Primary CPC classification H03D7/1441. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 09 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).