Esd protection circuit for i/o buffer

Patent metadata

Field	Value
Publication number	US-2021281066-A1
Application number	US-202016999958-A
Country	US
Kind code	A1
Filing date	Aug 21, 2020
Priority date	Mar 4, 2020
Publication date	Sep 9, 2021
Grant date	—

Abstract

An ESD protection circuit for an input/output buffer in which when an ESD pulse or event occurs, an ESD surge on a pad is discharged to a diode and a transistor channel, thereby enhancing the efficiency of the ESD protection circuit. The ESD protection circuit includes a floating N-well bias circuit connected to a pad at an output of driver circuit and outputting a bias voltage based on or in response to a supply voltage; a switch circuit connected to a logic circuit and the driver circuit, and configured to connect and disconnect the logic circuit and the driver circuit based on or in response to the supply voltage; and a pull-down circuit connected to the driver circuit, configured to output a voltage to the driver circuit based on or in response to the supply voltage.

First claim

What is claimed is:

1 . An ESD protection circuit for an input/output buffer including a logic circuit and a driver circuit, the ESD protection circuit comprising:
a floating N-well bias circuit connected to a pad at an output of the driver circuit, the floating N-well bias circuit having an output voltage based on or in response to a supply voltage; a switch circuit connected to the logic circuit and the driver circuit, the switch circuit configured to switch a connection between the logic circuit and the driver circuit based on or in response to the supply voltage; and a pull-down circuit connected to the driver circuit, the pull-down circuit outputting a voltage to the driver circuit based on or in response to the supply voltage.

2 . The ESD protection circuit of claim 1 , wherein the output voltage of the floating N-well bias circuit is a floating N-well bias voltage, and
the floating N-well bias circuit is configured to output the supply voltage as the floating N-well bias voltage during normal operation.

3 . The ESD protection circuit of claim 1 , wherein the output voltage of the floating N-well bias circuit is a floating N-well bias voltage, and
the floating N-well bias circuit is configured to output a voltage on the pad as the floating N-well bias voltage when the supply voltage is at or near a ground potential.

4 . The ESD protection circuit of claim 1 , wherein the switch circuit connects the logic circuit and a pulldown node to the driver circuit when the supply voltage is in a normal range.

5 . The ESD protection circuit of claim 1 , wherein the switch circuit disconnects the logic circuit and the pulldown node when an ESD pulse or event occurs.

6 . The ESD protection circuit of claim 1 , wherein the pull-down circuit operates in a sleep mode when the supply voltage is in a normal range.

7 . The ESD protection circuit of claim 1 , wherein the pull-down circuit outputs a ground potential or a voltage of 0 V to a pullup node of the driver circuit when an ESD pulse or event occurs.

8 . A floating N-well bias circuit connected to a driver circuit, the floating N-well bias circuit comprising:
a first PMOS transistor having a gate receiving a supply voltage and a source connected to a pad at an output of the driver circuit; a second PMOS transistor having a gate connected to a drain of the first PMOS transistor, a source receiving the supply voltage, and a drain connected to an output of the floating N-well bias circuit; a third PMOS transistor having a gate receiving the supply voltage, a source connected to the pad, and a drain connected to the output of the floating N-well bias circuit; and a first NMOS transistor having (i) a gate receiving the supply voltage and (ii) a source connected to the drain of the first PMOS transistor and the gate of the second PMOS transistor.

9 . The floating N-well bias circuit of claim 8 , wherein when the supply voltage is in a normal range, the first NMOS transistor outputs a ground potential or a voltage of 0 V to the gate of the second PMOS transistor, and the second PMOS transistor outputs the supply voltage as the output of the floating N-well bias circuit.

10 . The floating N-well bias circuit of claim 8 , wherein when the supply voltage is at or near a ground potential, the first PMOS transistor outputs a voltage on the pad to the gate of the second PMOS transistor.

11 . The floating N-well bias circuit of claim 8 , wherein the third PMOS transistor outputs a voltage on the pad when the supply voltage is at or near a ground potential.

12 . A switch circuit configured to connect and disconnect a logic circuit and a driver circuit, the switch circuit comprising:
a PMOS transistor having a gate connected to a pad at an output of the driver circuit, a source connected to the logic circuit, and a drain connected to a gate of a first NMOS transistor in the driver circuit; and a second NMOS transistor having a gate receiving a supply voltage, a source connected to the logic circuit, and a drain connected to the driver circuit.

13 . The switch circuit of claim 12 , wherein when the supply voltage is in a normal range, the second NMOS transistor forms a path between a pulldown node to the driver circuit and the logic circuit and passes to the pulldown node an output of the logic circuit.

14 . The switch circuit of claim 12 , wherein when the supply voltage is at or near a ground potential, the NMOS transistor and the PMOS transistor are off, and an overlap capacitance between the pulldown node and the pad blocks or disconnects a current at or on the pulldown node from the logic circuit.

15 . A pull-down circuit comprising:
a first NMOS transistor having a source connected to a pullup node to a driver circuit of an input/output buffer; a second NMOS transistor having a gate receiving a supply voltage and a source connected to a gate of the first NMOS transistor; a first PMOS transistor having a source and a drain connected to a pad at an output of the driver circuit; and a second PMOS transistor having a gate receiving the supply voltage, a source connected to a gate of the first PMOS transistor, and a drain connected to the source of the second NMOS transistor and to the gate of the first NMOS transistor.

16 . The pull-down circuit of claim 15 , wherein when the supply voltage is in a normal range, the second NMOS transistor outputs a voltage of 0 V to the gate of the first NMOS transistor, and the first NMOS transistor disconnects the pullup node from a ground potential.

17 . The pull-down circuit of claim 15 , further comprising:
a resistor connected to the gate of the first PMOS transistor, wherein the first PMOS transistor and the resistor R 1 increase power to the source of the second PMOS transistor when an ESD pulse or event occurs.

18 . The pull-down circuit of claim 15 , wherein when the supply voltage is at or near a ground potential, the second PMOS transistor outputs a voltage on the pad to the first NMOS transistor.

19 . The pull-down circuit of claim 18 , wherein the first NMOS transistor is configured to output a ground potential or a voltage of 0 V to the pullup node when an ESD event occurs at the pad, and the pullup node is connected to a gate of a third PMOS transistor in the driver circuit.

20 . The pull-down circuit of claim 19 , wherein the first NMOS transistor transfers a current on or at the pad to a source of the supply voltage.

Assignees

• Db Hitek Co Ltd

Inventors

• Lee Sang-Mok
• Jang Joon-Tae
• Kim Seung-Hoo
• Cha Jae-Ah

Classifications

• H10D89/811 Primary

  using FETs as protective elements · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H03K17/08104 Primary

  in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence) · CPC title

• H03K19/0136

  by means of a pull-up or down element · CPC title

• H02H9/045 Primary

  adapted to a particular application and not provided for elsewhere · CPC title