Memory module with distributed data buffers

Patent metadata

Field	Value
Publication number	US-2021271593-A1
Application number	US-202117202021-A
Country	US
Kind code	A1
Filing date	Mar 15, 2021
Priority date	Jul 16, 2009
Publication date	Sep 2, 2021
Grant date	—

Abstract

A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive N-bit-wide data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. Each respective data buffer includes a n-bit-wide (n<N) data path and logic configurable to, in response to the second module control signals, enable the n-bit-wide data path to receive and regenerate signals carrying a respective n-bit-wide section of the N-bit-wide data communicated from/to a respective n-bit-wide section of the module data lines. The logic is further configurable to disable the n-bit-wide data path when the memory module is not being accessed for data.

First claim

We claim:

1 . A memory module operable in a computer system, the computer system including address and control signal lines, data signal lines, a plurality of module slots for mounting a plurality of memory modules, and a memory controller configurable to communicate with each of the plurality of memory modules via the address and control signal lines and the data signal lines, the plurality of memory modules including the memory module and one or more other memory modules, the memory module comprising:
a module board having an edge connector including a plurality of electrical contacts to be releasably coupled to corresponding contacts of a module slot of the plurality of module slots; memory devices arranged in multiple N-bit-wide ranks on the module board; a module controller on the module board configurable to receive via the address and control signal lines address and control signals corresponding to a memory read or write operation, and to output first module control signals and second module control signals in response to the memory read or write operation being targeted at one of the multiple N-bit-wide ranks, wherein, in response to the first module control signals, the one of the multiple N-bit-wide ranks performs the memory read or write operation by outputting or receiving N-bit-wide data associated with the memory read or write operation; and data buffers distributed along the edge connector of the module board and coupled to the memory devices via module data lines, each respective data buffer including a n-bit-wide data path and logic configurable to, in response to the second module control signals from the module controller, enable the n-bit-wide data path to receive and regenerate signals carrying a respective n-bit-wide section of the N-bit-wide data between a respective n-bit-wide section of the data signal lines and a respective n-bit-wide section of the module data lines, wherein n is less than N; wherein the n-bit-wide data path is disabled when any of the one or more other memory modules is performing a read or write operation with the memory controller.

2 . The memory module of claim 1 , wherein N is equal to 32, 64, 72, 128, or 256, and n is equal to 8, and wherein the respective n-bit-wide section of the module data lines is coupled to a respective n-bit-wide section of the memory devices, and wherein the respective n-bit-wide section of the memory devices includes one memory device having a bit width of 8 in each of the multiple N-bit-wide ranks or two memory devices each having a bit width of 4 in each of the multiple N-bit-wide ranks.

3 . The memory module of claim 1 , wherein the n-bit-wide data path includes read data paths and write data paths, and wherein:
the read or write operation is a read operation; the one of the multiple N-bit-wide ranks is configured to output the N-bit-wide data during the read operation; and the logic is configurable to enable the read data paths and to disable the write data paths during the read operation.

4 . The memory module of claim 3 , wherein:
the read data paths include input buffers configurable to receive the respective n-bit-wide section of the N-bit-wide data via the respective n-bit-wide section of the module data lines, and output buffers configurable to drive the signals carrying the respective n-bit-wide section of the N-bit-wide data onto the respective n-bit-wide section of the data signal lines; and the logic is configurable to enable the output buffers during the read operation and to disable at least the output buffers after the read operation.

5 . The memory module of claim 4 , wherein each of the output buffers is comparable to an output buffer in one of the memory devices so that the respective data buffer is configurable to present a load to the memory controller during the read operation that is the same as a load that one of the memory devices would present.

6 . The memory module of claim 1 , wherein the n-bit-wide data path includes read data paths and write data paths, and wherein:
the read or write operation is a write operation; the one of the multiple N-bit-wide ranks of the multiple N-bit-wide ranks is configured to receive the N-bit-wide data via the respective n-bit-wide section of the module data lines during the write operation; and the logic is configurable to enable the write data paths and to disable the read data paths during the write operation.

7 . The memory module of claim 6 , wherein:
the write data paths include input buffers configurable to receive the respective n-bit-wide section of the N-bit-wide data via the respective n-bit-wide section of the data signal lines, and output buffers configurable to drive the signals carrying the respective n-bit-wide section of the N-bit-wide data onto the respective n-bit-wide section of the module data lines; and the logic is configurable to enable the output buffers during the write operation and to disable the output buffers after the write operation.

8 . The memory module of claim 7 , wherein each of the input buffers is comparable to an input buffer in one of the memory devices so that the respective data buffer is configurable to present a load to the memory controller during the write operation that is the same as a load that one of the memory devices would present.

9 . The memory module of claim 6 , wherein each of the module data lines is configurable to carry data from the memory controller to a corresponding memory device in each of the multiple N-bit-wide ranks.

10 . The memory module of claim 1 , wherein the n-bit-wide data path includes first tristate buffers configurable to drive signals carrying read data to the respective n-bit-wide section of the data signal lines and second tristate buffers configurable to drive signals carrying write data to the respective n-bit-wide section of the module data lines, and wherein the logic is configurable to disable the n-bit-wide data path by setting an output of each of the first tristate buffers and the second tristate buffers to a high-impedance state.

11 . The memory module of claim 1 , wherein the module controller is configurable to control the data buffers in accordance with a CAS latency parameter.

12 . The memory module of claim 1 , wherein the data buffers are configurable to tristate outputs coupled to the data signal lines and/or outputs coupled to the module data lines when the memory module is not accessed by the memory controller for memory read or write operations.

13 . The memory module of claim 1 , wherein each of the memory devices is selected from the group consisting of a dynamic random-access memory, synchronous dynamic random-access memory, and double-data-rate dynamic random-access memory.

14 . A method, comprising:
at a memory module operable in a computer system, the computer system including address and control signal lines, data signal lines, a plurality of module slots for mounting a plurality of memory modules, and a memory controller configurable to communicate with each of the plurality of memory modules via the address and control signal lines and the data signal lines, the plurality of memory modules including the memory module and one or more other memory modules, the memory module including a module board having an edge connector comprising a plurality of electrical contacts to be releasably coupled to corresponding contacts of the module slot, a module controller on the module board, memory devices arranged in multiple N-bit-wide ranks on the module board and coupled to the module controller, and data buffers distributed along the edge of the module board and coupled to

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R

Classifications

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C5/02 Primary

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G06F12/00 Primary

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G11C5/066

  Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals · CPC title