Arithmetic logic unit, multiply-accumulate operation device, multiply-accumulate operation circuit, and multiply-accumulate operation system

Patent metadata

Field	Value
Publication number	US-2021271453-A1
Application number	US-201917258309-A
Country	US
Kind code	A1
Filing date	Jul 5, 2019
Priority date	Jul 17, 2018
Publication date	Sep 2, 2021
Grant date	—

Abstract

An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Electrical signals are input to the plurality of input lines. The multiply-accumulate operation device includes a pair of output lines, a plurality of multiplication units including a weight unit that generates, on the basis of the electrical signals input to the plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on the basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines, an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units, and an output unit that outputs, on the basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.

First claim

1 . An arithmetic logic unit, comprising:
a plurality of input lines, electrical signals being input to the plurality of input lines; and a multiply-accumulate operation device that includes
a pair of output lines,
a plurality of multiplication units including a weight unit that generates, on a basis of the electrical signals input to the plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on a basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines,
an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units, and
an output unit that outputs, on a basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.

2 . The arithmetic logic unit according to claim 1 , wherein
the weight unit includes a MOS transistor including an input terminal, an output terminal, and a gate terminal for controlling conduction between the input terminal and the output terminal.

3 . The arithmetic logic unit according to claim 2 , wherein
the weight value is set by a resistance between the input terminal and the output terminal.

4 . The arithmetic logic unit according to claim 2 , wherein
the holding unit includes a first terminal and a second terminal that switch and output, on a basis of the held binary state, two types of voltages so that the voltages differ from each other.

5 . The arithmetic logic unit according to claim 4 , wherein
the gate terminal is connected to the input line, and the input terminal is connected to one of the first terminal, the second terminal, and a predetermined constant voltage source.

6 . The arithmetic logic unit according to claim 4 , wherein
the input terminal is connected to the input line, and the gate terminal is connected to one of the first terminal, the second terminal, and a predetermined gate voltage source.

7 . The arithmetic logic unit according to claim 2 , wherein
the weight unit includes a first MOS transistor and a second MOS transistor connected to the same input line, and the switch unit includes the first and second MOS transistors.

8 . The arithmetic logic unit according to claim 2 , wherein
the pair of output lines includes a first output line and a second output line, and the switch unit include a first switch element that connects the output terminal and the first output line to each other and a second switch element that connects the output terminal and the second output line to each other.

9 . The arithmetic logic unit according to claim 2 , wherein
the holding unit is connected to the input terminal, and the weight unit outputs a control signal for controlling the binary state of the holding unit from the input terminal.

10 . The arithmetic logic unit according to claim 1 , wherein
the weight unit generates charges corresponding to a multiplication value obtained by multiplying the signal value by an absolute value of the weight value, and the holding unit holds a binary state corresponding to a sign of the weight value.

11 . The arithmetic logic unit according to claim 1 , wherein
the weight value is set to one of a first value and a second value having equal absolute values and different signs in the plurality of multiplication units.

12 . The arithmetic logic unit according to claim 1 , wherein
the plurality of input lines includes pairs of the input lines, each of the pairs including a first input line and a second input line, and the multiplication unit includes a first weight unit connected to the first input line and a second weight unit connected to the second input line, of the pair of input lines.

13 . The arithmetic logic unit according to claim 12 , wherein
the multiplication unit includes a first switch unit that outputs, on a basis of the held binary state, charges generated by the first weight unit to one of the pair of output lines, and a second switch unit that outputs, on a basis of the held binary state, charges generated by the second weight unit to the other of the pair of output lines.

14 . The arithmetic logic unit according to claim 1 , wherein
the weight unit includes a high-resistance element that controls an amount of charges corresponding to the multiplication value.

15 . The arithmetic logic unit according to claim 1 , wherein
the weight unit includes a MOS transistor that operates in a subthreshold region.

16 . The arithmetic logic unit according to claim 1 , further comprising
a plurality of the multiply-accumulate operation devices connected in parallel to each of the plurality of input lines.

17 . The arithmetic logic unit according to claim 16 , wherein
the plurality of input lines is wired so as to cross a plurality of pairs of the output lines included in the plurality of multiply-accumulate operation devices.

18 . The arithmetic logic unit according to claim 1 , wherein
the electrical signal is a signal representing the signal value by timing within an input period or a pulse width, the multiply-accumulate operation device includes a charging unit that charges the accumulation unit at a constant charging speed in an output period after the input period, and the output unit outputs the multiply-accumulate signal by performing threshold determination on a potential of the accumulation unit in the output period.

19 . The arithmetic logic unit according to claim 18 , wherein
the charging unit connects the accumulation unit to the pair of output lines in the input period, and connects the accumulation unit to a current source in the output period, the current source supplying a current corresponding to the constant charging speed.

20 . The arithmetic logic unit according to claim 18 , wherein
the charging unit connects the accumulation unit to a GND before the input period.

21 . A multiply-accumulate operation device, comprising:
a pair of output lines; a plurality of multiplication units that includes a weight unit that generates, on a basis of electrical signals input to a plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on a basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines; an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units; and an output unit that outputs, on a basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.

22 . A multiply-accumulate operation circuit, comprising:
a pair of output lines; a plurality of multiplication units that includes a weight unit that generates, on a basis of electrical signals input to a plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on a basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines; an accumulation

Assignees

• Sony Corp

Inventors

• Morie Takashi
• Yamaguchi Masatoshi
• TAMUKOH Hakaru

Classifications

• G06N3/065

  Analogue means · CPC title

• G06G7/161 Primary

  with pulse modulation, e.g. modulation of amplitude, width, frequency, phase or form {(pulse modulators H03K7/00)} · CPC title

• G06G7/16

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• H03K17/30

  Modifications for providing a predetermined threshold before switching (shaping pulses by thresholding H03K5/08) · CPC title