Arithmetic device

Patent metadata

Field	Value
Publication number	US-10175947-B1
Application number	US-201815899723-A
Country	US
Kind code	B1
Filing date	Feb 20, 2018
Priority date	Sep 15, 2017
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-side current source, a negative-side current source, M cross switches, a coefficient memory unit, and a comparator. The positive-side current source is configured to output a first voltage corresponding to a value of 1/L of the current output from a positive-side terminal. The negative-side current source is configured to output a second voltage corresponding to a value of 1/L of the current output from a negative-side terminal. The memory unit includes M cells corresponding to the respective M coefficients. The comparator is configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage. Each M cell includes a first resistor and a second resistor.

First claim

What is claimed is:

1. An arithmetic device configured to receive M input signals each representing a two-state value and M coefficients corresponding respectively to the M input signals to output an output signal representing a two-state value where M is an integer larger than or equal to 2, the device comprising:
a positive-side current source configured to output a current from a positive-side terminal, and output a first voltage corresponding to a value of 1/L of the current output from the positive-side terminal where L is an integer equal to or larger than 2;
a negative-side current source configured to output a current from a negative-side terminal, and output a second voltage corresponding to a value of 1/L of the current output from the negative-side terminal;
M cross switches that are provided corresponding to the respective M input signals;
a coefficient memory unit including M cells corresponding to the respective M coefficients; and
a comparator configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage,
each of the M cells includes a first resistor and a second resistor,
one end of the first resistor is connected to a first terminal of a corresponding cross switch,
the other end of the first resistor is connected to a first reference potential,
one end of the second resistor is connected to a second terminal of a corresponding cross switch, and
the other end of the second resistor is connected to the first reference potential.

2. The device according to claim 1 , wherein
a magnitude relation of resistance values of the first resistor and the second resistor is changed according to a value of a corresponding coefficient, and
each of the M cross switches switches over whether to connect the first terminal and the second terminal to the positive-side terminal and the negative-side terminal by straight connection or reverse connection according to a value of a corresponding input signal.

3. The device according to claim 2 , further comprising a setting unit configured to receive the M coefficients, each representing a two-state value, prior to reception of the M input signals, and set a magnitude relation of resistance values of the first resistor and the second resistor included in a corresponding cell according to a corresponding one of the received M coefficients.

4. The device according to claim 2 , wherein either one of the first resistor and the second resistor is set to a first resistance value according to a value of a corresponding coefficient, and the other resistor is set to a second resistance value different from the first resistance value.

5. The device according to claim 2 , wherein one of the first resistor and the second resistor is a fixed resistor, and the other resistor is a variable resistor.

6. The device according to claim 2 , wherein at least one of the first resistor and the second resistor is a resistive random access memory.

7. The device according to claim 2 , wherein
in case of the straight connection, each of the M cross switches connects the first terminal with the positive-side terminal, and the second terminal with the negative-side terminal, and
in case of the reverse connection, each of the M cross switches connects the first terminal with the negative-side terminal, and the second terminal with the positive-side terminal.

8. The device according to claim 1 , wherein
the positive-side current source includes L first FETs,
gates of the L first FETs are commonly connected, sources of the L first FETs are connected to a second reference potential, and drains of the L first FETs are connected to the gate and the positive-side terminal,
the negative-side current source includes L second FETs, and
gates of the L second FETs are commonly connected, sources of the L second FETs are connected to the second reference potential, and drains of the L second FETs are connected to the gate and the negative-side terminal.

9. The device according to claim 8 , wherein the L first FETs and the L second FETs have identical characteristics.

10. The device according to claim 8 , wherein
the positive-side current source outputs a voltage of the positive-side terminal as the first voltage, and
the negative-side current source outputs a voltage of the negative-side terminal as the second voltage.

11. The device according to claim 1 , wherein when the first voltage is smaller than the second voltage, the comparator outputs the output signal having a first value, and when the first voltage is equal to or larger than the second voltage, the comparator outputs the output signal having a second value.

12. The device according to claim 1 , further comprising a selector configured to select any one of N word addresses, wherein
the coefficient memory unit includes the M cells for N sets corresponding respectively to the N word addresses,
each of the M cells further includes
a first switch configured to switch over connection or disconnection between the first resistor and the first terminal or between the first resistor and the first reference potential, and

a second switch configured to switch over connection or disconnection between the second resistor and the second terminal or between the second resistor and the first reference potential, and
the selector connects between the first switch and the second switch included in a cell corresponding to a selected word address, and disconnects the first switch and the second switch from each other included in other cells.

Assignees

• Toshiba Kk

Inventors

• Marukame Takao
• Ueda Yoshihiro
• Miyano Shinji
• Yasuda Shinichi
• Nishi Yoshifumi
• Matsumoto Mari

Classifications

• G06F7/57 Primary

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F7/487

  Multiplying; Dividing {(G06F7/4833, G06F7/4836 take precedence)} · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title