Via-via spacing reduction without additional cut mask

Patent metadata

Field	Value
Publication number	US-2021265166-A1
Application number	US-202016795718-A
Country	US
Kind code	A1
Filing date	Feb 20, 2020
Priority date	Feb 20, 2020
Publication date	Aug 26, 2021
Grant date	—

Abstract

A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

First claim

1 . A method for employing double-patterning to reduce via-to-via spacing, the method comprising:
forming a mandrel layer over a substrate; forming sacrificial hardmask layers over the mandrel layer defining a litho stack; creating a pattern in the litho stack having a narrow section connecting two wider sections; depositing a spacer assuming a shape of the pattern; and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

2 . The method of claim 1 , wherein the metal lines include vias.

3 . The method of claim 2 , wherein a distance between the vias is reduced.

4 . The method of claim 3 , wherein the distance between the metal lines and the distance between the vias is reduced without an additional masking layer.

5 . The method of claim 1 , wherein the distance between the sharp distal ends of the metal lines defines a jogged area.

6 . The method of claim 5 , wherein the spacer is merged in the jogged area.

7 . The method of claim 6 , wherein the jogged area enables isolation between the sharp distal ends of the metal lines.

8 . The method of claim 7 , wherein tip-to-tip rules and tip-to-side rules are defined by the deposition of the spacer.

9 . The method of claim 1 , wherein the reduced distance between the metal lines is defined by the deposition of the spacer.

10 . The method of claim 1 , wherein the spacer electrically isolates the sharp distal ends of the metal lines.

11 . A method for employing double-patterning to reduce via-to-via spacing without an additional masking layer, the method comprising:
creating a pattern in a litho stack formed over a substrate, the pattern having a narrow section connecting two wider sections; depositing a spacer assuming a shape of the pattern; and etching the litho stack to expose metal lines defining sharp distal ends reducing a distance between the metal lines.

12 . The method of claim 11 , wherein the distance between the sharp distal ends of the metal lines defines a jogged area.

13 . The method of claim 12 , wherein the spacer is merged in the jogged area.

14 . The method of claim 13 , wherein the jogged area enables isolation between the sharp distal ends of the metal lines.

15 . The method of claim 14 , wherein tip-to-tip rules and tip-to-side rules are defined by the deposition of the spacer.

16 . The method of claim 11 , wherein the reduced distance between the metal lines is defined by the deposition of the spacer.

17 . The method of claim 11 , wherein the spacer electrically isolates the sharp distal ends of the metal lines.

18 . A semiconductor structure for employing double-patterning to reduce via-to-via spacing without an additional masking layer, the semiconductor structure comprising:
a pair of sharp tip-to-tip oriented metal lines with a via disposed at respective distal ends; and a spacer disposed between the pair of sharp tip-to-tip oriented metal lines, wherein the spacer is pinched off between the pair of sharp tip-to-tip oriented metal lines to electrically isolate the pair of sharp tip-to-tip oriented metal lines.

19 . The semiconductor structure of claim 18 , wherein a distance between the pair of sharp tip-to-tip oriented metal lines define a jogged area.

20 . The semiconductor structure of claim 19 , wherein the spacer is merged in the jogged area.

Assignees

• IBM

Inventors

• Dechene Daniel James
• Ghosh Somnath
• Chen Hsueh-Chung
• Radens Carl
• Clevenger Lawrence A

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H01L21/0335

  Electricity · mapped topic

• H01L21/0337

  Electricity · mapped topic