Method of forming structures including a vanadium or indium layer

US2021242011A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2021242011-A1
Application numberUS-202117162279-A
CountryUS
Kind codeA1
Filing dateJan 29, 2021
Priority dateFeb 3, 2020
Publication dateAug 5, 2021
Grant date

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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Methods and systems for depositing vanadium and/or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and/or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and/or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and/or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

First claim

Opening claim text (preview).

1 . A method of forming a structure, the method comprising the steps of: providing a substrate within a reaction chamber of a reactor; and using a cyclical deposition process, depositing a layer comprising one or more of vanadium and indium onto a surface of the substrate, wherein the cyclical deposition process comprises: providing one or more of a vanadium precursor and an indium precursor to the reaction chamber; and providing one or more of an oxygen reactant, a nitrogen reactant, a sulfur reactant, and a carbon reactant to the reaction chamber. 2 . The method of claim 1 , wherein the vanadium precursor comprises one or more of a vanadium halide, a vanadium oxyhalide, a vanadium organometallic compound, and a vanadium metal organic compound. 3 . The method of claim 1 , wherein the indium precursor comprises one or more of an indium alkyl compound, an indium cyclopentadienyl compound, an indium beta-diketonate compound, and an indium acetate compound. 4 . The method of claim 1 , wherein the structure comprises a threshold voltage tuning layer comprising the layer comprising one or more of vanadium and indium. 5 . The method of claim 1 , wherein the structure comprises a p-dipole shifter layer comprising the layer comprising one or more of vanadium and indium. 6 . The method of claim 1 , wherein the structure comprises a gate all around structure. 7 . The method of claim 6 , wherein the gate all around structure includes a high-k dielectric layer. 8 . The method of claim 1 , wherein the cyclical deposition process comprises a cyclical chemical vapor deposition process. 9 . The method of claim 1 , wherein the cyclical deposition process comprises a thermal process. 10 . The method of claim 1 , wherein a thickness of the layer comprising one or more of vanadium and indium is between about 0.1 nm and about 5 nm. 11 . The method of claim 1 , wherein the one or more of a vanadium precursor and an indium precursor comprises a halide and the step of providing one or more of an oxygen reactant, a nitrogen reactant, a sulfur reactant, and a carbon reactant to the reaction chamber comprises providing the oxygen reactant. 12 . The method of claim 1 , wherein the vanadium precursor comprises a beta-diketonate compound. 13 . The method of claim 1 , wherein the reactant comprises the oxygen reactant. 14 . The method of claim 1 , wherein the structure comprises a barrier layer comprising the layer comprising one or more of vanadium and indium. 15 . The method of claim 1 , wherein the structure comprises an etch stop layer comprising the layer comprising one or more of vanadium and indium. 16 . A structure comprising the layer comprising one or more of vanadium and indium formed according to the method of claim 1 . 17 . The structure of claim 16 , comprising a high-k dielectric layer overlying a semiconductor material. 18 . The structure of claim 17 , wherein the layer comprising one or more of vanadium and indium is overlying and in contact with the high-k dielectric layer. 19 . The structure of claim 16 , wherein a thickness of the layer comprising one or more of vanadium and indium is less than 5 nm. 20 . The structure of claim 16 , wherein the layer comprising one or more of vanadium and indium comprises one or more of vanadium nitride and vanadium carbon nitride. 21 . A gate all around device comprising the structure of claim 16 . 22 . The gate all around device of claim 21 , wherein the layer comprising one or more of vanadium and indium comprises one or more of a vanadium oxide and an indium oxide. 23 . A metal oxide semiconductor (MOS) device comprising the structure of claim 16 . 24 . A DRAM device comprising the structure of claim 16 . 25 . A logic device comprising the structure of claim 16 . 26 . A 3DNAND device comprising the structure of claim 16 . 27 . A system comprising: one or more reaction chambers; a precursor gas source comprising one or more of a vanadium precursor and an indium precursor; a reactant gas source comprising one or more of an oxygen reactant, a nitrogen reactant, a sulfur reactant, and a carbon reactant; an exhaust source; and a controller, wherein the controller is configured to control gas flow into at least one of the one or more reaction chambers to form a layer comprising one or more of vanadium and indium overlying a surface of a substrate using a cyclical deposition process.

Assignees

Inventors

Classifications

  • characterised by the metal · CPC title

  • deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

  • using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

  • the material containing two or more metal elements · CPC title

  • the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides · CPC title

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What does patent US2021242011A1 cover?
Methods and systems for depositing vanadium and/or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and/or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and/or indium precursor to …
Who is the assignee on this patent?
Asm Ip Holding Bv
What technology area does this patent fall under?
Primary CPC classification H10P14/6339. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Aug 05 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).