Low-power compute-in-memory bitcell

Patent metadata

Field	Value
Publication number	US-2021240442-A1
Application number	US-202016779491-A
Country	US
Kind code	A1
Filing date	Jan 31, 2020
Priority date	Jan 31, 2020
Publication date	Aug 5, 2021
Grant date	—

Abstract

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.

First claim

We claim:

1 . A compute-in-memory storage cell, comprising:
a pair of cross-coupled inverters having a first output node for a stored bit; a read bit line; a word line having a voltage responsive to an input bit; a capacitor having a first plate connected to the read bit line; and a first pass transistor connected between the first output node and a second plate of the capacitor and having a gate connected to the word line.

2 . The compute-in-memory storage cell of claim 1 , wherein the pair of cross-coupled inverters include a second output node for a complement of the stored bit; the compute-in-memory storage cell further comprising:
a complement word line having a voltage responsive to a complement of the input bit; a second pass transistor connected between the second output node and the second plate of the capacitor and having a gate connected to the complement word line.

3 . The compute-in-memory storage cell of claim 2 , wherein the first pass transistor and the second pass transistor are both p-type metal-oxide semiconductor (PMOS) transistors.

4 . The compute-in-memory storage cell of claim 2 , further comprising:
a read word line; and a third transistor connected between the second plate of the capacitor and ground and having a gate connected to the read word line.

5 . The compute-in-memory storage cell of claim 4 , wherein the third transistor is an n-type metal-oxide semiconductor (NMOS) transistor having a source connected to ground and a drain connected to the second plate of the capacitor.

6 . The compute-in-memory storage cell of claim 4 , further comprising:
a fourth transistor connected between a power supply node for a power supply voltage and the read bit line.

7 . The compute-in-memory storage cell of claim 6 , wherein the fourth transistor is a PMOS transistor having a source connected to the power supply node and a drain connected to the read bit line.

8 . The compute-in-memory storage cell of claim 7 , further comprising:
a reset line for a reset signal, wherein a gate for the fourth transistor is connected to the reset line.

9 . The compute-in-memory storage cell of claim 2 , further comprising:
a write bit line; a complement write bit line: a first access transistor connected between the write bit line and the first output node; and a second access transistor connected between the complement write bit line and the second output node.

10 . The compute-in-memory storage cell of claim 9 , further comprising:
a write word line, wherein the write word line is connected to a gate of the first access transistor and is connected to a gate of the second access transistor.

11 . The compute-in-memory storage cell of claim 6 , further comprising a fifth transistor connected between the second plate of the capacitor and the power supply node.

12 . The compute-in-memory storage cell of claim 1 , wherein the compute-in-memory storage cell is included within a column in an array of compute-in-memory storage cells.

13 . The compute-in-memory storage cell of claim 1 , wherein the capacitor is selected from the group consisting of a metal-layer capacitor, a varactor, and a metal-insulator-metal capacitor.

14 . The compute-in-memory storage cell of claim 5 , wherein the third transistor is a thick-oxide transistor.

15 . A compute-in-memory storage cell, comprising:
a pair of cross-coupled inverters having a first output node for a stored bit; a read bit line; a capacitor having a first plate connected to the read bit line; and a first transmission gate connected between the first output node and a second plate of the capacitor, wherein the first transmission gate is configured to close in response to an input bit being true and is configured to open in response to the input bit being false.

16 . The compute-in-memory storage cell of claim 15 , wherein the pair of cross-coupled inverters include a second output node for a complement of the stored bit; the compute-in-memory storage cell further comprising:
a second transmission gate connected between the second output node and the second plate of the capacitor, wherein the second transmission gate is configured to open in response to the input bit being true and is configured to close in response to the input bit being false.

17 . The compute-in-memory storage cell of claim 15 , wherein the input bit is an active-low signal.

18 . The compute-in-memory storage cell of claim 15 , further comprising:
a read word line; and a first transistor connected between the second plate of the capacitor and ground and having a gate connected to the read word line.

19 . The compute-in-memory storage cell of claim 18 , wherein the first transistor is a n-type metal-oxide semiconductor (NMOS) transistor having a source connected to ground and a drain connected to the second plate of the capacitor.

20 . The compute-in-memory storage cell of claim 18 , further comprising:
a second transistor connected between a power supply node for a power supply voltage and the read bit line.

21 . The compute-in-memory storage cell of claim 20 , wherein the second transistor is a PMOS transistor having a source connected to the power supply node and a drain connected to the read bit line.

22 . The compute-in-memory storage cell of claim 21 , further comprising:
a reset line for a reset signal, wherein a gate for the second transistor is connected to the reset line.

23 . A multiply-and-accumulate circuit, comprising:
a plurality of compute-in-memory storage cells arranged into a plurality of columns, wherein each column includes a read bit line, and wherein each compute-in-memory storage cell in each column includes a logic gate configured to multiply an input bit with a stored bit and includes a capacitor having a first plate connected to the column's read bit line and having a second plate connected to an output node for the logic gate.

24 . The multiply-and-accumulate circuit of claim 23 , further comprising:
a plurality of analog-to-digital converters corresponding to the plurality of columns on a one-to-one basis, each analog-to-digital converter configured to convert a voltage for the corresponding column's read bit line into a digital value.

25 . The multiply-and-accumulate circuit of claim 24 , wherein each analog-to-digital converter is a multi-bit analog-to-digital converter.

26 . The multiply-and-accumulate circuit of claim 24 , wherein each analog-to-digital converter is a successive-approximation-register analog-to-digital converter including a digital-to-analog converter.

27 . The multiply-and-accumulate circuit of claim 24 , further comprising:
a plurality of sequential integrators corresponding to the plurality of columns on a one-to-one basis, wherein each sequential integrator is configured to integrate the digital value from the corresponding column's analog-to-digital converter.

28 . The multiply-and-accumulate circuit of claim 23 , wherein each logic gate is an exclusive not- or (XNOR) logic gate.

29 . The multiply-and-accumulate circuit of claim 23 , wherein each logic gate is an exclusive or (XOR) logic gate.

30 . The multiply-and-accumulate circuit of claim 23 , wherein the multiply-and-accumulate circuit is integrated into a mobile device.

31 . T

Assignees

• Qualcomm Inc

Inventors

• Srivastava Ankit
• Mirhaj Seyed Arash
• Miao Guoqing
• Bazarjani Seyfi

Classifications

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title