Circuits and methods for in-memory computing

Patent metadata

Field	Value
Publication number	US-11355167-B2
Application number	US-202117356211-A
Country	US
Kind code	B2
Filing date	Jun 23, 2021
Priority date	Dec 24, 2018
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments. With one analog-to-digital converter (ADC) per column, the macro cab realize fully parallel vector-matrix multiplication in a single cycle in accordance with some embodiments.

First claim

What is claimed is:

1. A circuit for a bitcell, comprising:
a first switch having a first side, a second side, and a control input wherein the first side of the first switch is connected to a first supply voltage;
a second switch having a first side, a second side, and a control input wherein the control input of the second switch is connected to the second side of the first switch, and the second side of the second switch is connected to the control input of the first switch;
a third switch having a first side, a second side, and a control input wherein the first side of the third switch is connected to the second side of the first switch, the second side of the third switch is connected to a second supply voltage, and the control input of the third switch is connected to the control input of the first switch;
a fourth switch having a first side, a second side, and a control input wherein the first side of the fourth switch is connected to the second side of the second switch, the second side of the fourth switch is connected to the second supply voltage, and the control input of the fourth switch is connected to the control input of the second switch;
a fifth switch having a first side, a second side, and a control input wherein the first side of the fifth switch is connected to the second side of the first switch;
a sixth switch having a first side, a second side, and a control input wherein the first side of the sixth switch is connected to the second side of the second switch and the control input of the sixth switch is connected to the control input of the fifth switch;
a seventh switch having a first side, a second side, and a control input wherein the control input of the seventh switch is connected to the second side of the first switch;
an eighth switch having a first side, a second side, and a control input wherein the control input of the eighth switch is connected to the second side of the second switch; and
a first capacitor having a first side and a second side wherein the first side of the first capacitor is connected to the first side of the seventh switch and the first side of the eighth switch.

2. The circuit of claim 1 , further comprising
a ninth switch having a first side, a second side, and a control input wherein the first side of the ninth switch is connected to the first supply voltage;
a tenth switch having a first side, a second side, and a control input wherein the control input of the tenth switch is connected to the second side of the ninth switch, and the second side of the tenth switch is connected to the control input of the ninth switch;
an eleventh switch having a first side, a second side, and a control input wherein the first side of the eleventh switch is connected to the second side of the ninth switch, the second side of the eleventh switch is connected to the second supply voltage, and the control input of the eleventh switch is connected to the control input of the ninth switch;
a twelfth switch having a first side, a second side, and a control input wherein the first side of the twelfth switch is connected to the second side of the tenth switch, the second side of the twelfth switch is connected to the second supply voltage, and the control input of the twelfth switch is connected to the control input of the tenth switch;
a thirteenth switch having a first side, a second side, and a control input wherein the first side of the thirteenth switch is connected to the second side of the ninth switch and the second side of the thirteenth switch is connected to the second side of the fifth switch;
a fourteenth switch having a first side, a second side, and a control input wherein the first side of the fourteenth switch is connected to the second side of the tenth switch, the control input of the fourteenth switch is connected to the control input of the thirteenth switch, the second side of the fourteenth switch is connected to the second side of the sixth switch;
a fifteenth switch having a first side, a second side, and a control input wherein the control input of the fifteenth switch is connected to the second side of the ninth switch;
a sixteenth switch having a first side, a second side, and a control input wherein the control input of the sixteenth switch is connected to the second side of the tenth switch; and
a second capacitor having a first side and a second side wherein the first side of the second capacitor is connected to the first side of the fifteenth switch and the first side of the sixteenth switch.

3. The circuit of claim 2 , wherein the second side of the second capacitor is connected to the second side of the first capacitor and wherein during a first time period the first side of the first capacitor, the first side of the second capacitor, the second side of the first capacitor, and the second side of the second capacitor are all connected to a reset voltage.

4. The circuit of claim 2 , wherein the second side of the second capacitor is connected to the second side of the first capacitor and wherein during a second time period the first side of the first capacitor is connected to a third supply voltage and the first side of the second capacitor is connected to the second supply voltage.

5. The circuit of claim 4 , wherein the third supply voltage is less than the first supply voltage and greater than the second supply voltage.

6. The circuit of claim 5 , wherein the first supply voltage is higher than the third supply voltage by an amount greater than a threshold voltage of the seventh transistor.

7. The circuit of claim 2 , further comprising
a seventeenth switch having a first side, a second side, and a control input wherein the first side of the seventeenth switch is connected to the first supply voltage;
a eighteenth switch having a first side, a second side, and a control input wherein the control input of the eighteenth switch is connected to the second side of the seventeenth switch, and the second side of the eighteenth switch is connected to the control input of the seventeenth switch;
a nineteenth switch having a first side, a second side, and a control input wherein the first side of the nineteenth switch is connected to the second side of the seventeenth switch, the second side of the nineteenth switch is connected to the second supply voltage, and the control input of the nineteenth switch is connected to the control input of the seventeenth switch;
a twentieth switch having a first side, a second side, and a control input wherein the first side of the twentieth switch is connected to the second side of the eighteenth switch, the second side of the twentieth switch is connected to the second supply voltage, and the control input of the twentieth switch is connected to the control input of the eighteenth switch;
a twenty first switch having a first side, a second side, and a control input wherein the first side of the twenty first switch is connected to the second side of the seventeenth switch and the control input of the twenty first switch is connected to the control input of the fifth switch and to the control input of the sixth switch;
a twenty second switch having a first side, a second side, and a control input wherein the first side of the a twenty second switch is connected to the second side of the eighteenth switch and the control input of the twenty second switch is connected to the control input of the twenty first switch;
a twenty third switch having a first side, a second side, and a control input wherein the control input of the twenty third switch is connected to the second side of the seventeenth switch;
a twenty fourth switch having a first side, a second side, and a control input wherein the control input of the twenty fourth switch is connected to the second side of the

Assignees

• Univ Columbia

Inventors

• Seok Mingoo
• Jiang Zhewei
• Seo Jae-Sun
• Yin Shihui

Classifications

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C7/1036 Primary

  using data shift registers · CPC title