Method for manufacturing transistor

Patent metadata

Field	Value
Publication number	US-2021226143-A1
Application number	US-202117168830-A
Country	US
Kind code	A1
Filing date	Feb 5, 2021
Priority date	Aug 8, 2018
Publication date	Jul 22, 2021
Grant date	—

Abstract

A method for manufacturing a transistor being a bottom-gate transistor is provided. The method for manufacturing a transistor includes a step of forming a first metal layer 32 on an insulator layer 20 provided on a substrate 10 including a gate electrode, a step of applying a resist onto the first metal layer 32 , and patterning the first metal layer 32 by a photolithographic method, an oxide film removal step of removing an oxide film 26 formed on the patterned first metal layer 32 , and a step of forming a source electrode and a drain electrode by forming a second metal layer 42 on the first metal layer 32.

First claim

What is claimed is:

1 . A method for manufacturing a transistor being a bottom-gate transistor, the method comprising:
a step of forming a first metal layer on an insulator layer provided on a substrate including a gate electrode or on a semiconductor layer provided on a substrate including a gate electrode and an insulator layer; a patterning step of applying a resist onto the first metal layer, and patterning the first metal layer by a photolithographic method; an oxide film removal step of removing an oxide film formed on the patterned first metal layer; and a step of forming a source electrode and a drain electrode by forming a second metal layer on the first metal layer after the oxide film removal step.

2 . The method for manufacturing a transistor according to claim 1 , further comprising:
a drying step of drying the substrate after the patterning step of patterning the first metal layer, wherein the oxide film removal step is performed after the drying step.

3 . The method for manufacturing a transistor according to claim 1 , wherein
the first metal layer is formed by first electroless plating.

4 . The method for manufacturing a transistor according to claim 1 , wherein
the second metal layer is formed by second electroless plating.

5 . The method for manufacturing a transistor according to claim 1 , wherein
a metal material of the first metal layer is nickel-phosphorus.

6 . The method for manufacturing a transistor according to claim 1 , wherein
a metal material of the second metal layer is gold.

7 . The method for manufacturing a transistor according to claim 1 , wherein
an energy level difference between a work function of a metal material used for the second metal layer and an energy level of a molecular orbital used for an electron movement in a formation material of the semiconductor layer is smaller than an energy level difference between a work function of a metal material used for the first metal layer and the energy level of the molecular orbital.

8 . The method for manufacturing a transistor according to claim 1 , wherein
the oxide film is removed by bringing the patterned first metal layer into contact with an acid solution in the oxide film removal step.

9 . The method for manufacturing a transistor according to claim 1 , wherein
the semiconductor layer is formed of an organic semiconductor.

10 . A method for manufacturing a transistor being a top-gate transistor, the method comprising:
a step of forming a first metal layer on a substrate or on a semiconductor layer provided on a substrate; a patterning step of applying a resist onto the first metal layer, and patterning the first metal layer by a photolithographic method; an oxide film removal step of removing an oxide film formed on the patterned first metal layer; and a step of forming a source electrode and a drain electrode by forming a second metal layer on the first metal layer after the oxide film removal step.

11 . The method for manufacturing a transistor according to claim 10 , further comprising:
a drying step of drying the substrate after the patterning step of patterning the first metal layer, wherein the step of removing the oxide film is performed after the drying step.

12 . The method for manufacturing a transistor according to claim 10 , wherein
the first metal layer is formed by first electroless plating.

13 . The method for manufacturing a transistor according to claim 10 , wherein
the second metal layer is formed by second electroless plating.

14 . The method for manufacturing a transistor according to claim 10 , wherein
a metal material of the first metal layer is nickel-phosphorus.

15 . The method for manufacturing a transistor according to claim 10 , wherein
a metal material of the second metal layer is gold.

16 . The method for manufacturing a transistor according to claim 10 , wherein
an energy level difference between a work function of a metal material used for the second metal layer and an energy level of a molecular orbital used for an electron movement in a formation material of the semiconductor layer is smaller than an energy level difference between a work function of a metal material used for the first metal layer and the energy level of the molecular orbital.

17 . The method for manufacturing a transistor according to claim 10 , wherein
the oxide film is removed by bringing the patterned first metal layer into contact with an acid solution in the oxide film removal step.

18 . The method for manufacturing a transistor according to claim 10 , wherein
the semiconductor layer is formed of an organic semiconductor.

Assignees

• Nikon Corp

Inventors

• Koizumi Shohei

Classifications

• H10P14/46

  using a liquid · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H01L51/0545 Primary

  Electricity · mapped topic

• H01L51/105

  Electricity · mapped topic