Lithography Method With Reduced Impacts of Mask Defects

Patent metadata

Field	Value
Publication number	US-2021208505-A1
Application number	US-202117206722-A
Country	US
Kind code	A1
Filing date	Mar 19, 2021
Priority date	Jul 28, 2017
Publication date	Jul 8, 2021
Grant date	—

Abstract

An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.

First claim

What is claimed is:

1 . A method for extreme ultraviolet lithography (EUVL), the method comprising:
receiving an integrated circuit (IC) design layout; determining candidate sub-regions based on the IC design layout; determining sub-region parameters Nx and Ny and a mask parameter M based on a manufacturing cost function and the candidate sub-regions; and fabricating a first number of identical masks according to the IC design layout, wherein the first number equals to the mask parameter M, wherein each of the masks includes Nx times Ny sub-regions configured in an array, wherein each of the sub-regions on each of the masks defines a same pattern.

2 . The method of claim 1 , wherein the manufacturing cost function is defined as a function of a mask fabrication cost and a lithography exposure cost.

3 . The method of claim 2 , wherein the mask fabrication cost further includes a mask making cost, a blank mask cost, and a mask repair cost; and
wherein the lithography exposure cost is a function of a stepping time cost and a scanning time cost.

4 . The method of claim 1 , further comprising:
forming a resist layer on a substrate; and performing a second number of exposure processes to a same area of the resist layer using the masks, wherein the second number equals to M*Nx′*Ny′, wherein each of the exposure processes uses only one of the masks, wherein the exposure processes includes M groups paired with the first number of masks so that each group of the exposure processes is implemented using a paired mask, wherein each group of the exposure processes further includes Nx′*Ny′ exposure processes using a respective sub-region of the paired mask, and wherein the second number of the exposure processes collectively form a latent image of the pattern in the area of the resist layer, wherein Nx′ is an integer with a value 1, 2, . . . , or Nx, and Ny′ is an integer with a value 1, 2, . . . , or Ny., wherein Nx′*Ny′ is greater than one.

5 . The method of claim 4 , further comprising developing the resist layer to form a patterned resist having the pattern in the area.

6 . The method of claim 4 , further comprising determining an optimized exposure dose Eop for the resist layer.

7 . The method of claim 6 , wherein the area of the resist layer is exposed M*Nx′*Ny′ times by the second number of the exposure processes with respective exposure doses, each being less than optimized exposure dose.

8 . The method of claim 7 , wherein the respective exposure doses from the exposure processes add up to an accumulative exposure dose Es that is equals to the optimized exposure dose Eop.

9 . The method of claim 8 , wherein the respective exposure dose equals to Eop/M*Nx′*Ny′.

10 . A method comprising:
providing an integrated circuit (IC) pattern; determining a first number of available sub-regions based on the IC pattern; using a manufacturing cost function to determine a cost to manufacture based on the first number of available sub-regions; determining a second number of masks to fabricated based on the cost, wherein each of the second number of masks includes an array of mask sub-regions, wherein each of the masks in the array is identical to each of the other masks in the array; and fabricating the second number of masks.

11 . The method of claim 10 , wherein the manufacturing cost function further include:
a mask fabrication cost including a blank mask cost, a mask patterning cost, and a mask repair cost; and a photolithography cost including scanning time cost and stepping time cost.

12 . The method of claim 11 , wherein the manufacturing cost function further includes a mask complexity cost.

13 . The method of claim 11 , wherein the blank mask cost of a mask having a defect is lower than the blank mask cost of a mask free of defects; and
wherein a lower blank mask cost associated with the mask having a defect offsets a higher photolithography cost caused by the mask having a defect.

14 . The method of claim 10 , wherein the pattern of each of the mask sub-regions in the array of mask sub-regions is defined by the IC pattern.

15 . A method comprising:
determining a first number of candidate sub-regions of an integrated circuit (IC) design layout; determining a second number of masks for use in a photolithography process; determining an array of mask sub-regions for each of the second number of masks, wherein the second number of masks and the array of mask sub-regions is based on a manufacturing cost function; and fabricating the array of mask sub-regions in each of the second number of masks, wherein each mask sub-region in the array of mask sub-regions of a mask is identical to each of the other mask sub-regions in the array of mask sub-regions.

16 . The method of claim 15 , wherein the manufacturing cost function further include:
a mask fabrication cost including a blank mask cost, a mask patterning cost, and a mask repair cost; and a photolithography cost including scanning time cost and stepping time cost.

17 . The method of claim 16 , wherein the blank mask cost of a mask having a defect is lower than the blank mask cost of a mask free of defects; and
wherein a lower blank mask cost associated with the mask having a defect offsets a higher photolithography cost caused by the mask having a defect.

18 . The method of claim 15 , wherein the array of mask sub-regions includes at least one row of mask sub-regions and at least one column of mask sub-regions.

19 . The method of claim 15 , further comprising:
forming a resist layer on a substrate; and performing a third number of exposure processes to a same area of the resist layer using the masks, wherein the third number equals the second number of masks multiplied by the number of mask sub-regions in the array of mask sub-regions, wherein each of the exposure processes uses only one of the masks, wherein the exposure processes include a fourth number of paired masks so that each of the exposure processes is implemented using a paired mask, wherein the fourth number of paired masks is equal to twice the second number of masks, wherein each of the exposure processes further includes a fifth number exposure processes using a respective sub-region of the paired mask, and wherein the third number of the exposure processes collectively form a latent image of a pattern in the area of the resist layer.

20 . The method of claim 19 , wherein the fifth number of exposure processes is equal to number of mask sub-regions in the array of mask sub-regions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Shinn-Sheng
• Yu Ching-Fang
• Wang Wen-Chuan
• Hsu Ting-Hao
• Chin Sheng-Chi
• Yen Anthony

Classifications

• G03F7/70033

  by plasma extreme ultraviolet [EUV] sources · CPC title

• G03F7/2022 Primary

  Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure · CPC title

• G03F1/24 Primary

  Reflection masks; Preparation thereof · CPC title

• G03F7/203

  comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation · CPC title

• G03F7/70466

  Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature (stitching G03F7/70475) · CPC title