Semiconductor devices and methods of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-2021193539-A1
Application number	US-201916720603-A
Country	US
Kind code	A1
Filing date	Dec 19, 2019
Priority date	Dec 19, 2019
Publication date	Jun 24, 2021
Grant date	—

Abstract

In one example, a semiconductor device comprises a cavity substrate comprising a base and a sidewall to define a cavity, an electronic component on a top side of the base in the cavity, a lid over the cavity and over the sidewall, and a valve to provide access to the cavity, wherein the valve has a plug to provide a seal between a cavity environment and an exterior environment outside the cavity. Other examples and related methods are also disclosed herein.

First claim

1 . A semiconductor device, comprising:
a cavity substrate comprising a base and a sidewall to define a cavity; an electronic component on a top side of the base in the cavity; a lid over the cavity and over the sidewall; and a valve to provide access to the cavity, wherein the valve has a plug to provide a seal between a cavity environment and an exterior environment outside the cavity.

2 . The semiconductor device of claim 1 , further comprising a seal base in the sidewall and a seal between the seal base and the lid.

3 . The semiconductor device of claim 1 , wherein the cavity environment comprises a vacuum.

4 . The semiconductor device of claim 1 , wherein the cavity environment comprises an inert gas.

5 . The semiconductor device of claim 1 , wherein the valve is coupled through the sidewall of the cavity substrate to the cavity.

6 . The semiconductor device of claim 1 , wherein the valve is between the sidewall of the cavity substrate and the lid.

7 . The semiconductor device of claim 1 , wherein the valve comprises an aperture in the base of the cavity substrate.

8 . The semiconductor device of claim 1 , wherein the valve comprises a groove in the sidewall of the cavity substrate between the sidewall and the lid.

9 . The semiconductor device of claim 1 , wherein the valve comprises a through-hole in the lid between the lid and the sidewall of the cavity substrate.

10 . The semiconductor device of claim 1 , wherein the plug comprises solder.

11 . The semiconductor device of claim 1 , wherein the plug comprises a resin.

12 . The semiconductor device of claim 1 , wherein the valve comprises a dam, and the plug is positioned in the dam.

13 . The semiconductor device of claim 1 , wherein the valve comprises a tap and the plug occludes the tap.

14 . The semiconductor device of claim 1 , further comprising a conductive structure in the base electrically coupled with the electronic component.

15 . A method, comprising:
providing a cavity substrate comprising a base and a sidewall to define a cavity; providing an electronic component on a top side of the base in the cavity; providing a lid over the cavity contacting the sidewall; and providing a valve to provide access to the cavity, wherein the valve has a plug to provide a seal between a cavity environment and an environment outside the cavity.

16 . The method of claim 15 , further comprising removing air from the cavity through the valve to provide a vacuum in the cavity environment prior to sealing the plug in the valve, and then sealing the plug in the valve.

17 . The method of claim 15 , further comprising adding an inert gas into the cavity through the valve prior to sealing the plug in the valve, and then sealing the plug in the valve.

18 . The method of claim 15 , further comprising sealing the plug in the valve using a laser.

19 . A semiconductor device, comprising:
a substrate comprising a base and a sidewall extending vertically from the base; a lid over the sidewall to define a cavity between the base, the sidewall, and the lid; an electronic component in the cavity; a valve between the cavity and an exterior environment outside the cavity; a seal between the lid and the sidewall; and a plug in the valve, wherein the seal and the plug hermetically seal the cavity from the exterior environment.

20 . The semiconductor device of claim 19 , wherein:
the valve includes a first through-hole and a second through-hole coupled to each other; a width of the second through-hole is greater than a width of the first through-hole; and the plug is in the second through-hole.

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Hanada shojiro
• Nakamura Shingo

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W76/43

  Gaseous fillings · CPC title