Storage device and method of operating the same

Patent metadata

Field	Value
Publication number	US-2021191636-A1
Application number	US-202016918521-A
Country	US
Kind code	A1
Filing date	Jul 1, 2020
Priority date	Dec 24, 2019
Publication date	Jun 24, 2021
Grant date	—

Abstract

A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on completion pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages included in the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

First claim

What is claimed is:

1 . A memory controller configured to control a memory device including a memory block coupled to physical word lines each including a plurality of pages, the memory controller comprising:
a program sequence information storage configured to store program sequence information of the plurality of pages; and a program controller configured to control the memory device such that, in response to a power off event occurring while a program operation is performed on a selected page among the plurality of pages, fine program operations are performed, based on the program sequence information, on to-be-completed pages, that are pages which precede the selected page, and on which foggy program operations have been completed and on which the fine program operations have not yet been performed.

2 . The memory controller according to claim 1 , wherein each of the to-be-completed pages is included in a physical word line different from a physical word line including the selected page.

3 . The memory controller according to claim 1 , wherein the program controller is further configured to control the memory device to perform a dummy program operation of storing dummy data in a boundary page included in a physical word line adjacent to a physical word line including the selected page.

4 . The memory controller according to claim 3 , wherein the program operation includes:
the foggy program operation of programming memory cells included in the plurality of pages so that each of the memory cells has a threshold voltage corresponding to any one of intermediate states respectively corresponding to a plurality of states, and the fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each of the memory cells has a threshold voltage corresponding to any one of the plurality of states.

5 . The memory controller according to claim 4 , wherein the program controller controls the memory device to perform the foggy program operation for the dummy program operation and skip the fine program operation for the dummy program operation.

6 . The memory controller according to claim 3 , wherein a number of boundary pages corresponds to a number of the plurality of pages.

7 . The memory controller according to claim 3 , wherein the program controller is further configured to store power off information after the dummy program operation is completed.

8 . The memory controller according to claim 7 , further comprising a power off information storage configured to store the power off information.

9 . The memory controller according to claim 7 , wherein the power off information includes at least one of information about the selected page on which the program operation is interrupted due to the power off event, information about the boundary page, and information about pages included in a physical word line on which a program operation is to be performed in a sequence subsequent to the physical word line including the selected page.

10 . A memory device comprising:
a memory block coupled to physical word lines each including a plurality of pages; a peripheral circuit configured to perform a program operation of storing data in the plurality of pages; a control logic configured to control the peripheral circuit, wherein the program operation includes: a foggy program operation of programming memory cells included in the plurality of pages so that each of the memory cells has a threshold voltage corresponding to any one of intermediate states respectively corresponding to a plurality of states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each of the memory cells has a threshold voltage corresponding to any one of the plurality of states, and wherein the control logic controls the peripheral circuit to perform the foggy program operation on one page of a plurality of pages included in a selected physical word line among the physical word lines and then perform the fine program operation on one page of a plurality of pages included in a physical word line on which the foggy program operation has been performed in a sequence preceding the selected physical word line.

11 . The memory device according to claim 10 ,
wherein the foggy program operation and the fine program operation each includes a plurality of program loops, wherein each of the plurality of program loops includes a program voltage application operation and a verify operation, and wherein a level of a verify voltage to be used in the verify operation of the foggy program operation is less than a level of a verify voltage to be used in the verify operation of the fine program operation.

12 . The memory device according to claim 10 , wherein the plurality of pages included in each physical word line is coupled in common to the physical word line.

13 . The memory device according to claim 10 , wherein each of the physical word lines comprises logical word lines respectively coupled to the plurality of pages.

14 . The memory device according to claim 10 , wherein the control logic controls the peripheral circuit to further perform, in response to a power off event in which power supply to the memory device is interrupted, the fine program operation on each of to-be-completed pages, that are pages which precede a page on which the program operation is interrupted due to the power off event, and on which the foggy program operations have been completed and on which the fine program operations have not yet been performed.

15 . The memory device according to claim 10 , wherein the control logic controls the peripheral circuit to further perform, in response to a power off event in which power supply to the memory device is interrupted, a dummy program operation of storing dummy data in a boundary page that is a page included in a physical word line adjacent to a physical word line including a page on which the program operation is interrupted due to the power off event.

16 . The memory device according to claim 15 , wherein a number of boundary pages corresponds to a number of the plurality of pages.

17 . The memory device according to claim 15 , wherein the control logic controls the peripheral circuit to perform the foggy program operation for the dummy program operation and skip the fine program operation for the dummy program operation.

18 . The memory device according to claim 14 , wherein each of the to-be-completed pages is a page included a physical word line different from the selected physical word line.

19 . A storage device comprising:
a memory device comprising a memory block coupled to physical word lines each including a plurality of pages; and a memory controller configured to control the memory device such that, in response to a power off event occurring while a program operation is performed on a selected page among the plurality of pages, fine program operations are performed on to-be-completed pages, that are pages which precede the selected page, and on which foggy program operations have been completed and on which the fine program operations have not yet been performed, wherein the program operation includes: the foggy program operation of programming memory cells included in the plurality of pages so that each of the memory cells has a threshold voltage corresponding to any one of intermediate states respectively corresponding to a plurality of states, and the f

Assignees

• Sk Hynix Inc

Inventors

• Ji Seung Gu
• Rho Jun Rye

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title