Semiconductor storage device and memory system

Patent metadata

Field	Value
Publication number	US-2018075902-A1
Application number	US-201715459542-A
Country	US
Kind code	A1
Filing date	Mar 15, 2017
Priority date	Sep 13, 2016
Publication date	Mar 15, 2018
Grant date	—

Abstract

According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

First claim

1 . A semiconductor storage device comprising:
a first memory cell capable of storing n-bit data (n is a natural number not less than 4), wherein when first data including first and second bits of the n-bit data is received from a controller, the received first data is written to the first memory cell, after the first data is received, when second data including third and fourth bits of the n-bit data is received, the first and second bits are read from the first memory cell, and the n-bit data is written to the first memory cell based on the read first and second bits and the received second data.

2 . The device of claim 1 , further comprising:
a second memory cell capable of storing the n-bit data and connected to the first memory cell, wherein third data including the first and second bits is received between writing of the received first data and reception of the second data, and the received third data is written to the second memory cell.

3 . The device of claim 1 , further comprising:
a word line connected to the first memory cell, wherein when the n-bit data is written based on the read first and second bits and the received second data, first to third read voltage different from each other are applied in sequence before application of an initial program pulse to the word line to read the first and second bits of the first data.

4 . The device of claim 3 , wherein
when the received first data is written, a first program pulse is applied a plurality of times to the word line, wherein a voltage of the first program pulse increases, from a first voltage, by a second voltage for each application of the first program pulse, when the n-bit data is written based on the read first and second bits and the received second data, a second program pulse is applied a plurality of times to the word line, wherein a voltage of the second program pulse increases, from a third voltage, by a fourth voltage for each application of the second program pulse, the first voltage is higher than the third voltage, and the second voltage is higher than the fourth voltage.

5 . The device of claim 3 , wherein
in a read operation, fourth to eighteenth read voltages different from each other are applied to the word line to read the n-bit data from the first memory cell, and the first read voltage is different from the fourth to eighteenth read voltages.

6 . The device of claim 1 , further comprising:
a word line connected to the first memory cell, wherein the first data further includes the third bit, when the received first data is written, first to fifth verify voltages are applied to the word line, and writing of the received first data is ended when all verifications according to the first to fifth verify voltages have been passed.

7 . A memory system comprising:
the semiconductor storage device and the controller according to claim 1 , wherein the controller includes a memory retaining write data including the first and second data, and the memory clears the first data when the first data retained in the memory is transferred to the semiconductor storage device.

8 . A memory system comprising:
the semiconductor storage device and the controller according to claim 1 , wherein the controller is connectable to a host apparatus, the n-bit data is stored based on a threshold voltage of the first memory cell, the controller assigns the n-bit data to the threshold voltage of the first memory cell, based on a first code and a second code different from the first code, the controller applies the first code to data received from the host apparatus and converts data to which the first code is applied from the first code to the second code, and the semiconductor storage device writes data, converted to the second code, to the first memory cell.

9 . The memory system of claim 8 , wherein
the controller gives an error correction code to data to which the first code is applied before converting the data to which the first code is applied to the second code.

10 . The memory system of claim 9 , wherein
in a read operation, n-bit data written to the first memory cell is read collectively.

11 . The memory system of claim 10 , wherein
in the read operation, the semiconductor storage device transfers the n-bit data, read from the first memory cell, to the controller, and the controller converts the transferred data from the second code to the first code and applies error correction to the data, converted to the first code, based on the error correction code.

12 . A semiconductor storage device comprising:
a first memory cell being capable of storing n-bit data (n is a natural number not less than 4), wherein when first data including first to third bits of the n-bit data is received from a controller, the received first data is written to the first memory cell, after the first data is received, when second data including fourth bit of the n-bit data is received, the first data is read from the first memory cell, and the n-bit data is written to the first memory cell based on the read first data and the transferred second data.

13 . The device of claim 12 , further comprising:
a second memory cell being capable of storing the n-bit data and connected to the first memory cell, wherein third data including the first to third bits is received between writing of the received first data and reception of the second data, and the received third data is written to the second memory cell.

14 . The device of claim 12 , further comprising:
a word line connected to the first memory cell, wherein when the n-bit data is written based on the read first data and the received second data, first to seventh read voltages different from each other are applied in sequence before application of an initial program pulse to the word line to read the first data from the first memory cell.

15 . The device of claim 14 , wherein
when the transferred first data is written, a first program pulse is applied a plurality of times to the word line, wherein a voltage of the first program pulse increases, from a first voltage, by a second voltage for each application of the first program pulse, when the n-bit data is written based on the read first data and the transferred second data, a second program pulse is applied a plurality of times to the word line, wherein a voltage of the second program pulse increases, from a third voltage, by a fourth voltage for each application of the second program pulse, the first voltage is higher than the third voltage, and the second voltage is higher than the fourth voltage.

16 . The device of claim 14 , wherein
in a read operation, fourth to eighteenth read voltages different from each other are applied to the word line to read the n-bit data from the first memory cell, and the first read voltage is different from the fourth to eighteenth read voltages.

17 . A memory system comprising:
the semiconductor storage device and the controller according to claim 12 , wherein the controller includes a memory retaining write data including the first and second data, and the memory clears the first data when the first data retained in the memory is transferred to the semiconductor storage device.

18 . A memory system comprising:
the semiconductor storage device and the controller according to claim 12 , wherein the controller is connected to a host apparatus, the n-bit data is stored based on a threshold voltage of the first memory cell, the controller assigns the n-bit data to the threshold v

Assignees

• Toshiba Memory Corp

Inventors

• Shirakawa Masanobu
• Akamine Takayuki

Classifications

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G06F11/1072

  in multilevel memories · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title