Method for fabricating tft array substrate

Patent metadata

Field	Value
Publication number	US-2021183913-A1
Application number	US-202016933801-A
Country	US
Kind code	A1
Filing date	Jul 20, 2020
Priority date	Dec 11, 2019
Publication date	Jun 17, 2021
Grant date	—

Abstract

A method of fabricating a thin-film transistor (TFT) array substrate including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a source electrode and a drain electrode comprising a plurality of metal layer patterns on the ohmic contact layer, in which the semiconductor layer, the ohmic contact layer, the source electrode and the drain electrode are formed through a single mask process, and one of the plurality of metal layer patterns is etched through a polishing process to form the source electrode and the drain electrode.

First claim

What is claimed is:

1 . A method of fabricating a thin-film transistor (TFT) array substrate, the method comprising:
forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; and forming a source electrode and a drain electrode comprising a plurality of metal layer patterns on the ohmic contact layer, wherein the semiconductor layer, the ohmic contact layer, the source electrode, and the drain electrode are formed through a single mask process, and wherein one of the plurality of metal layer patterns is etched through a polishing process to form the source electrode and the drain electrode.

2 . The method of claim 1 , wherein the gate electrode is formed using a first mask.

3 . The method of claim 1 , wherein forming the semiconductor layer, the source electrode, and the drain electrode comprises:
stacking a first amorphous silicon layer, a second amorphous silicon layer, a second metal layer, and a third metal layer on the substrate; forming a photoresist pattern on the third metal layer using a second mask; and etching the first amorphous silicon layer, the second amorphous silicon layer, the second metal layer, and the third metal layer to form the semiconductor layer, the ohmic contact layer, the source electrode, and the drain electrode.

4 . The method of claim 3 , wherein the second mask includes a transmissive region through which light is transmitted, a non-transmissive region through which light is blocked, and a transflective region through which an amount of transmitted light is adjusted.

5 . The method of claim 4 , wherein the photoresist pattern includes a first photoresist region in line with the non-transmissive region and a second photoresist region in line with the transflective region.

6 . The method of claim 5 , wherein a thickness of the second photoresist region is less than a thickness of the first photoresist region.

7 . The method of claim 6 , wherein forming the source electrode and the drain electrode comprises:
wet etching the second metal layer and the third metal layer by using the photoresist pattern as a mask to form a second metal layer pattern and a third metal layer pattern; ashing the photoresist pattern to remove the second photoresist region and reduce the thickness of the first photoresist region to form a third photoresist region; wet etching the third metal layer pattern not overlapping with the third photoresist region to form a fourth metal layer pattern; and etching the second metal layer pattern not overlapping with the third photoresist region via a polishing process to form a fifth metal layer pattern, such that the source electrode and the drain electrode including the fourth metal layer pattern and the fifth metal layer pattern stacked one over another are formed.

8 . The method of claim 7 , further comprising, prior to ashing the photoresist pattern, simultaneously dry etching the first amorphous silicon layer and the second amorphous silicon layer using the photoresist pattern as a mask to form the first amorphous silicon layer as a semiconductor pattern and the second amorphous silicon layer as an ohmic pattern.

9 . The method of claim 8 , wherein after forming the source electrode and the drain electrode, the ohmic pattern and the semiconductor pattern may be dry etched using the photoresist pattern as a mask to form the ohmic contact layer and the semiconductor layer.

10 . The method of claim 1 , further comprising, after forming the source electrode and the drain electrode, forming a passivation layer over the substrate and forming a via hole exposing the drain electrode using a third mask; and
forming a pixel electrode on the passivation layer by using a fourth mask.

11 . The method of claim 1 , wherein the polishing process comprises applying a polishing slurry onto the substrate and polishing one of the plurality of metal layer patterns using a polishing apparatus including a polishing pad.

12 . The method of claim 11 , wherein the polishing slurry includes polishing particles, and an average particle diameter of the polishing particles is in a range from 0.1 μm to 5 μm.

13 . The method of claim 11 , wherein an acidity (pH) of the polishing slurry is in a range from 2 to 8.

14 . The method of claim 11 , wherein the polishing pad includes suede or polyurethane.

15 . The method of claim 11 , wherein the polishing apparatus applies a polishing pressure to press the substrate, and a polishing pressure is in a range from 100 Pa to 300 Pa.

16 . A method of fabricating a thin-film transistor (TFT) array substrate, the method comprising:
forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; and forming a source electrode and a drain electrode on the ohmic contact layer by etching through a polishing process, wherein the polishing process comprises applying a polishing slurry onto the substrate and etching the source electrode and the drain electrode by using a polishing apparatus including a polishing pad.

17 . The method of claim 16 , wherein the polishing slurry has a negative zeta potential, and the source and drain electrodes have a positive zeta potential at a same pH value.

18 . The method of claim 16 , wherein the polishing slurry includes polishing particles, and an average particle diameter of the polishing particles is in a range from 0.1 μm to 5 μm.

19 . The method of claim 16 , wherein an acidity (pH) of the polishing slurry is in a range from 2 to 8.

20 . The method of claim 16 , wherein the polishing apparatus applies a polishing pressure to press the substrate, and a polishing pressure is in a range from 100 Pa to 300 Pa.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Hong Beom
• Kwon Chang Woo

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D86/0231 Primary

  using masks, e.g. half-tone masks · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title