Stacked dies and methods for forming bonded structures

Patent metadata

Field	Value
Publication number	US-2021183847-A1
Application number	US-202017131329-A
Country	US
Kind code	A1
Filing date	Dec 22, 2020
Priority date	May 19, 2016
Publication date	Jun 17, 2021
Grant date	—

Abstract

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

First claim

1 . (canceled)

2 . A method for forming a bonded structure, the method comprising:
mounting a first singulated integrated device die to a carrier; after mounting, thinning the first integrated device die; providing a protective material comprising a first layer on the first integrated device die; and after providing the protective material, exposing a conductive via that extends through the first singulated integrated device die.

3 . The method of claim 2 , wherein exposing the conductive via comprises removing at least a portion of the first layer.

4 . The method of claim 2 , wherein exposing the conductive via comprises removing at least a portion of a backside of the first singulated integrated device die.

5 . The method of claim 2 , wherein providing the first layer comprises depositing the first layer around the electrical interconnect.

6 . The method of claim 2 , wherein providing the protective material comprises providing a second layer on the first layer and removing at least a portion of the second layer.

7 . The method of claim 2 , wherein the first layer comprises a silicon-based dielectric or a polymer.

8 . The method of claim 2 , wherein the first layer is harder than the first integrated device die.

9 . The method of claim 2 , wherein providing the protective material comprises depositing the first layer to a thickness no less than a thickness of the first integrated device die, the thickness of the first integrated device die defined between a back surface and a front surface of the first integrated device die.

10 . The method of claim 9 , wherein the thickness of the first integrated device die is less than 20 microns.

11 . The method of claim 2 , further comprising directly bonding a second integrated device die to the first integrated device die without an intervening adhesive.

12 . The method of claim 11 , further comprising directly bonding a nonconductive portion of the second integrated device die to the first layer.

13 . The method of claim 2 , wherein providing the protective material comprises providing the first layer along at least a side surface of the first singulated integrated device die.

14 . The method of claim 13 , wherein providing the protective material comprises providing the first layer along a back surface of the first singulated integrated device die.

15 . The method of claim 2 , wherein exposing the conductive via comprises removing a portion of a liner from the conductive via.

16 . The method of claim 2 , further comprising providing a redistribution layer (RDL) over at least a portion of the protective material.

17 . The method of claim 16 , further comprising mounting a second integrated device die on the RDL.

18 . The method of claim 2 , further comprising singulating the carrier into a plurality of devices.

19 . A method for forming a bonded structure, the method comprising:
directly bonding a first singulated integrated device die to a redistribution layer (RDL) of a carrier without an intervening adhesive; directly bonding a second singulated integrated device to the RDL, the second singulated integrated device die laterally spaced apart from the first singulated integrated device die.

20 . The method of claim 19 , further comprising providing a protective material on the first integrated device die and the second integrated device die.

21 . The method of claim 20 , further comprising removing a portion of the protective material and exposing a conductive via.

22 . The method of claim 19 , further comprising directly bonding a first singulated integrated device die to the first integrated device die without an adhesive.

23 . A method for forming a bonded structure, the method comprising:
mounting a first integrated device die to a carrier, the first integrated device die having a first thickness; mounting a second integrated device die to a carrier, the second integrated device die having a second thickness different from the first thickness; providing a protective material over the first and second integrated device dies; and thinning the first and second integrated device dies.

24 . The method of claim 23 , wherein mounting the first integrated device die comprises directly bonding the first integrated device die to the carrier without an intervening adhesive.

25 . The method of claim 23 , wherein providing the protective material comprises providing a plurality of protective layers over the first and second integrated device dies.

26 . The method of claim 23 , wherein thinning the first and second integrated device dies comprises removing at least a portion of the protective material.

27 . The method of claim 23 , wherein at least one of the first and second thicknesses is in a range of 200 microns to 1000 microns.

28 . The method of claim 23 , wherein, after the thinning, the first and second integrated device dies have the same thickness.

Assignees

• Invensas Bonding Tech Inc

Inventors

• Uzoh Cyprian Emeka
• Sitaram Arkalgud R
• Enquist Paul

Classifications

• H10P72/70

  for supporting or gripping · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10W90/722

  between stacked chips · CPC title