Methods for removing an oxide film from a soi structure and methods for preparing a soi structure

Patent metadata

Field	Value
Publication number	US-2021183692-A1
Application number	US-202017085422-A
Country	US
Kind code	A1
Filing date	Oct 30, 2020
Priority date	Dec 13, 2019
Publication date	Jun 17, 2021
Grant date	—

Abstract

Methods for removing an oxide film from a silicon-on-insulator structure are disclosed. The oxide may be stripped from a SOI structure before deposition of an epitaxial silicon thickening layer. The oxide film may be removed by dispensing an etching solution toward a center region of the SOI structure and dispensing an etching solution to an edge region of the structure.

First claim

What is claimed is:

1 . A method for removing an oxide film from a silicon-on-insulator structure comprising:
providing a silicon-on-insulator structure having a handle structure, a silicon top layer and a dielectric layer disposed between the handle structure and the silicon layer, the silicon-on-insulator structure having an oxide film on a top surface of the silicon-on-insulator structure, the silicon-on-insulator structure having a radius R that extends from a center to a circumferential edge of the silicon-on-insulator structure; directing an etching solution to a center region of the top surface of the silicon-on-insulator structure while spinning the silicon-on-insulator structure; and directing an etching solution to an edge region of the top surface of the silicon-on-insulator structure while spinning the silicon-on-insulator structure, the edge region being disposed radially outward from the center region.

2 . The method as set forth in claim 1 wherein the center region extends from the center of the silicon-on-insulator structure to 0.1*R.

3 . The method as set forth in claim 1 wherein directing an etching solution to a center region of the top surface of the silicon-on-insulator structure comprises directing the etching solution to the center of the silicon-on-insulator structure.

4 . The method as set forth in claim 1 wherein the edge region begins at a distance 0.66*R from the center of the silicon-on-insulator structure and extends to the circumferential edge of the silicon-on-insulator structure.

5 . The method as set forth in claim 1 wherein the edge region begins at a distance 0.80*R from the center of the silicon-on-insulator structure and extends to the circumferential edge of the silicon-on-insulator structure.

6 . The method as set forth in claim 1 the etching solution comprises hydrofluoric acid and acetic acid, wherein the ratio of hydrogen fluoric acid (based on 49% basis) to acetic acid (glacial) in the etching solution is less than 1:1.

7 . The method as set forth in claim 1 wherein the flow of etching solution is stopped while the etching solution is being redirected from the center region to the edge region.

8 . The method as set forth in claim 1 wherein the etching solution is directed to the center region of the top surface of the silicon-on-insulator structure at a rate of 600 ml/min or less and the etching solution is directed to the edge region of the top surface of the silicon-on-insulator structure at a rate of 600 ml/min or less.

9 . The method as set forth in claim 1 wherein the etching solution is directed to the center region of the top surface of the silicon-on-insulator structure for 0.5 to 10 seconds.

10 . The method as set forth in claim 1 wherein the etching solution is directed to the edge region of the top surface of the silicon-on-insulator structure for 10 seconds to 20 minutes.

11 . The method as set forth in claim 1 wherein the etching solution directed to the center region has the same concentration as the etching solution directed to the edge region.

12 . The method as set forth in claim 1 wherein the etching solution directed to the center region has a different concentration that the etching solution directed to the edge region.

13 . The method as set forth in claim 1 wherein the etching solution directed to the center region and the etching solution directed to the edge region each comprising hydrogen fluoride and acetic acid.

14 . The method as set forth in claim 1 comprising moving a boom through which the etching solution is discharged to redirecting etching solution from the center region to the edge region.

15 . A method for preparing a silicon-on-insulator structure comprising a silicon top layer, a handle structure and dielectric layer disposed between the silicon top layer and handle structure, method comprising:
implanting ions into a donor structure to form a cleave plane in the donor structure; providing a handle structure; forming a dielectric layer on at least one of the donor structure and handle structure prior to bonding; bonding the donor structure to the handle structure to form a bonded wafer structure comprising the donor structure, handle structure and a dielectric layer disposed between the handle structure and the donor structure; cleaving the bonded wafer structure at the cleave plane such that a portion of the donor structure remains bonded to the handle structure as a silicon top layer, the cleave forming a silicon-on-insulator structure comprising the handle structure, silicon top layer and dielectric layer disposed between the handle layer and silicon top layer; annealing the silicon-on-insulator structure, an oxide forming on at least a top surface of the silicon-on-insulator structure during the anneal; contacting a center region of the top surface of the silicon-on-insulator structure with an etching solution while spinning the silicon-on-insulator structure; and contacting an edge region of the top surface of the silicon-on-insulator structure with the etching solution while spinning the silicon-on-insulator structure; and depositing an epitaxial silicon layer on the silicon top layer after contacting the center region and the edge region of the top surface of the silicon-on-insulator structure.

16 . The method as set forth in claim 15 comprising forming a dielectric layer on the handle structure prior to bonding.

17 . The method as set forth in claim 15 wherein the center region extends from the center of the silicon-on-insulator structure to 0.1*R.

18 . The method as set forth in claim 15 wherein directing an etching solution to a center region of the top surface of the silicon-on-insulator structure comprises directing the etching solution to the center of the silicon-on-insulator structure.

19 . The method as set forth in claim 15 wherein the edge region begins at a distance 0.85*R from the center of the silicon-on-insulator structure and extends to the circumferential edge of the silicon-on-insulator structure.

20 . The method as set forth in claim 15 wherein the flow of etching solution is stopped while the etching solution is being redirected from the center region to the edge region.

Assignees

• Globalwafers Co Ltd

Inventors

• Lottes Charles R
• Thomas Shawn George
• Erk Henry Frank

Classifications

• H10P70/15

  by wet cleaning only (H10P70/52 takes precedence) · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916 Primary

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title