Semiconductor Package and Method for Fabricating a Semiconductor Package

Patent metadata

Field	Value
Publication number	US-2021134708-A1
Application number	US-202017079587-A
Country	US
Kind code	A1
Filing date	Oct 26, 2020
Priority date	Nov 4, 2019
Publication date	May 6, 2021
Grant date	—

Abstract

A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a power semiconductor chip comprising SiC; a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part; and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

2 . The semiconductor package of claim 1 , wherein the power semiconductor chip is configured to operate at a temperature of 175° C. or more, or a temperature of 200° C. or more.

3 . The semiconductor package of claim 1 , wherein the solder joint comprises AgSnCu, AuSnCu, CuSn, NiSnCu, AgInCu, AuInCu, CuIn, or NiInCu.

4 . The semiconductor package of claim 1 , wherein the solder joint has a thickness of 10 μm or less.

5 . The semiconductor package of claim 1 , wherein the power semiconductor chip has a thickness of 200 μm or less, or 150 μm or less, or 100 μm or less.

6 . The semiconductor package of claim 1 , wherein a distance between a gate oxide of the power semiconductor chip and the leadframe part is 300 μm or less, or 200 μm or less, or 150 μm or less, or 100 μm or less, or 50 μm or less.

7 . The semiconductor package of claim 1 , further comprising:
a NiV layer arranged between the power semiconductor chip and the solder joint, wherein the NiV layer has a thickness of 300 nm or less.

8 . The semiconductor package of claim 1 , wherein the power semiconductor chip has a first main face, an opposite second main face and side faces connecting the first main face and the second main face, wherein the solder joint is arranged on the first main face and completely covers the first main face, and wherein the solder joint is flush with all side faces.

9 . A method for fabricating a semiconductor package, the method comprising:
providing a SiC semiconductor wafer comprising a plurality of power transistor circuits; depositing a first metal layer on the SiC semiconductor wafer; singulating the SiC semiconductor wafer into individual power semiconductor chips, each power semiconductor chip comprising at least one power transistor circuit; providing a leadframe part comprising Cu; arranging at least one of the power semiconductor chips on the leadframe part such that the first metal layer faces the leadframe part; and diffusion soldering the at least one power semiconductor chip to the leadframe part such that the first metal layer and the leadframe part form at least one intermetallic phase.

10 . The method of claim 9 , wherein the first metal layer comprises AgSn, AuSn, CuSn, NiSn, AgIn, AuIn, CuIn, or NiIn.

11 . The method of claim 9 , wherein depositing the first metal layer on the SiC semiconductor wafer comprises sputtering the first metal layer to a thickness of 1.2 μm or less.

12 . The method of claim 9 , wherein diffusion soldering the at least one power semiconductor chip to the leadframe part further comprises applying heat of 380° C. or more.

13 . The method of claim 9 , wherein diffusion soldering the at least one power semiconductor chip to the leadframe part further comprises pressing the at least one power semiconductor chip onto the leadframe part with a pressure of 4N/mm 2 or more.

14 . The method of claim 9 , wherein a bond line thickness after diffusion soldering is 4 μm or less.

15 . The method of claim 9 , wherein the at least one power semiconductor chip has a thickness of 150 μm or less.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Otremba Ralf
• Frank Paul
• Heinrich Alexander
• Ludsteck-Pechloff Alexandra
• Pedone Daniel

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title