Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

Patent metadata

Field	Value
Publication number	US-2021125919-A1
Application number	US-201916663683-A
Country	US
Kind code	A1
Filing date	Oct 25, 2019
Priority date	Oct 25, 2019
Publication date	Apr 29, 2021
Grant date	—

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

First claim

1 . A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers; first dummy pillars in the laterally-spaced memory blocks extending through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend; and second dummy pillars laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the laterally-spaced memory blocks, the second dummy pillars extending through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks.

2 . The memory array of claim 1 wherein the first dummy pillars extend through at least all of the insulative tiers and all of the conductive tiers through which the operative channel-material strings extend.

3 . The memory array of claim 1 wherein the second dummy pillars extend through at least all of the insulative tiers and all of the conductive tiers through which the operative channel-material strings extend.

4 . The memory array of claim 1 wherein the first and second dummy pillars extend through at least all of the insulative tiers and all of the conductive tiers through which the operative channel-material strings extend.

5 . The memory array of claim 1 wherein the first and second dummy pillars extend through the same insulative and conductive tiers.

6 . The memory array of claim 1 wherein the first and second dummy pillars have the same height.

7 . The memory array of claim 6 wherein the operative channel-material strings have common height relative one another and that is said same height.

8 - 17 . (canceled)

18 . A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, immediately-adjacent of the laterally-spaced memory blocks having a maximum lateral-separation distance of 120 to 220 nanometers in an uppermost of the insulative tiers; and dummy pillars in the laterally-spaced memory blocks extending through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend, the dummy pillars individually having a minimum horizontal width of 50 to 100 nanometers in the uppermost insulative tier.

19 - 20 . (canceled)

21 . A method used in forming a memory array comprising strings of memory cells, comprising:
forming a vertical stack comprising vertically-alternating first tiers and second tiers, the first tiers individually comprising void space, individual longitudinally-aligned dummy-pillar openings extending through the second tiers; forming conducting material in the void space of the first tiers by flowing the conducting material or one or more precursors thereof through the dummy-pillar openings to into the void space of the first tiers, the conducting material extending elevationally along the second tiers in individual of the dummy-pillar openings; after the forming of the conducting material, removing the conducting material from being elevationally along the second tiers in the individual dummy-pillar openings; after the removing, forming a dummy pillar in individual of the dummy-pillar openings; and forming operative channel-material strings of memory cells extending through the second tiers and the first tiers.

22 . The method of claim 21 comprising forming the operative channel-material strings before forming the dummy pillars.

23 . The method of claim 22 comprising forming the operative channel-material strings before the removing.

24 . The method of claim 23 comprising forming the operative channel-material strings before forming the conducting material.

25 . The method of claim 21 comprising forming channel openings through the second tiers and the first tiers in which the operative channel-material strings are formed, the channel openings and the dummy-pillar openings being formed at the same time.

26 . The method of claim 25 comprising filling the channel openings and the dummy-pillar openings with sacrificial material and there-after removing the sacrificial material from the channel openings and the dummy-pillar openings.

27 . The method of claim 26 wherein,
the filling of the channel openings and the dummy-pillar openings with the sacrificial material occurs at the same time; and
the removing of the sacrificial material from the channel openings and the dummy-pillar openings occurs at different times.

28 . The method of claim 27 wherein the removing of the sacrificial material from the channel openings occurs before the removing of the sacrificial material from the dummy-pillar openings.

29 . The method of claim 28 comprising forming channel material of the operative channel-material strings in the channel openings before the removing of the sacrificial material from the dummy-pillar openings.

30 . The method of claim 21 comprising forming and filling horizontally-elongated trenches in the vertical stack with intervening material to form laterally-spaced memory-block regions, said filling with intervening material occurring before forming the conducting material.

31 . The method of claim 30 wherein said filling with intervening material occurs before forming the void space in individual of the first tiers.

32 . The method of claim 21 wherein the vertical stack in a finished construction is formed to comprise:
a lower stack comprising vertically-alternating lower second tiers and lower first tiers, the lower stack comprising lower-laterally-spaced memory-block regions;
an upper stack directly above the lower stack, the upper stack comprising vertically-alternating upper second tiers and upper first tiers above the lower stack, the upper stack comprising upper-laterally-spaced memory-block regions that are directly above the lower-laterally-spaced memory-block regions;
the operative channel-material strings of the memory cells extending through the upper second tiers, the upper first tiers, the lower second tiers, and the lower first tiers; and
the dummy pillars extending through at least a majority of the upper second tiers, the upper first tiers, the lower second tiers, and the lower first tiers through which the operative channel-material strings extend.

33 . The method of claim 32 comprising forming additional dummy pillars laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the upper and lower memory-block regions, the additional dummy pillars extending through at least a majority of the upper second tiers, the upper first tiers, the lower second tiers, and the lower first tiers through which the operative channel-material strings extend.

34 . The method of claim 21 wherein forming the vertical stack comprises:
forming a lower stack comprising the vertically-alternating tiers;
forming a first portion of individual of the dummy-pillar openings in the lower stack;
filling the first portion with a sacrificial material

Assignees

• Micron Technology Inc

Inventors

• Machkaoutsan Vladimir
• Blomme Pieter
• Camerlenghi Emilio
• Dorhout Justin B
• Li Jian
• Meyer Ryan L
• Tessariol Paolo

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H01L23/5226 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic