Semiconductor deposition reactor manifolds

Patent metadata

Field	Value
Publication number	US-2021118668-A1
Application number	US-202017074887-A
Country	US
Kind code	A1
Filing date	Oct 20, 2020
Priority date	Oct 22, 2019
Publication date	Apr 22, 2021
Grant date	—

Abstract

The present disclosure pertains to embodiments of a semiconductor deposition reactor manifold and methods of using the semiconductor deposition reactor manifold which can be used to deposit semiconductor layers using processes such as atomic layer deposition (ALD). The semiconductor deposition reactor manifold has a bore, a first supply channel, and a second supply channel. Advantageously, the first supply channel and the second supply channel merge with the bore in an offset fashion which leads to reduced cross-contamination within the supply channels.

First claim

What is claimed is:

1 . A semiconductor processing device comprising:
a manifold comprising:
a bore configured to deliver vaporized reactant to a reaction chamber, the bore extending along a longitudinal axis;
an upper wall disposed at an upper portion of the manifold, the upper wall defining a capping surface at a first end of the bore along the longitudinal axis;
an outlet at a lower portion of the manifold along the longitudinal axis, the outlet configured to deliver gas to a reactor;
a first supply channel configured to supply gas to the bore; and
a second supply channel configured to supply gas to the bore,
wherein the first supply channel and the second supply channel merge with the bore at offset positions along the longitudinal axis.

2 . The semiconductor processing device of claim 1 , wherein the capping surface is shaped to redirect upwardly directed gas downwardly back through the bore to the outlet.

3 . The semiconductor processing device of claim 1 , further comprising a first block mounted to the manifold, the first block and the manifold cooperating to at least partially define the first supply channel.

4 . The semiconductor processing device of claim 3 , further comprising a second block mounted to the manifold, the second block and the manifold cooperating to at least partially define the second supply channel.

5 . The semiconductor processing device of claim 1 , wherein the first supply channel is in fluid communication with a first reactant source and is configured to deliver a first vaporized reactant to the bore, and wherein the second supply channel is in fluid communication with a second reactant source and is configured to deliver a second vaporized reactant to the bore.

6 . The semiconductor processing device of claim 1 , wherein the first supply channel is in fluid communication with an inactive gas to purge the bore.

7 . The semiconductor processing device of claim 1 , further comprising a showerhead device below the outlet, the showerhead device configured to disperse a flow of the gas from the outlet.

8 . The semiconductor processing device of claim 7 , further comprising a reaction chamber below the showerhead device and a substrate support configured to support a substrate in the reaction chamber.

9 . The semiconductor processing device of claim 3 , wherein the first block comprises a first vapor phase inlet configured to input a first reactant into the first supply channel.

10 . The semiconductor processing device of claim 9 , wherein the first block further comprises a second vapor phase inlet and a third vapor phase inlet.

11 . The semiconductor processing device of claim 10 , wherein the first block further comprises a fourth vapor phase inlet, wherein the fourth vapor phase inlet is located on a lateral side of the first block opposite to the manifold.

12 . The semiconductor processing device of claim 11 , wherein the fourth vapor phase inlet is configured to input a purge gas into the manifold.

13 . The semiconductor processing device of claim 1 , wherein the first supply channel is angled towards the capping surface and the second supply channel is angled towards the outlet, the second supply channel downstream of the first supply channel.

14 . The semiconductor processing device of claim 1 , wherein the manifold comprises a single monolithic block.

15 . The semiconductor processing device of claim 1 , wherein the bore extends continuously along the longitudinal axis.

16 . A semiconductor processing device comprising:
a manifold comprising a bore configured to deliver gas to a reaction chamber, the bore disposed along a longitudinal axis; an upper wall disposed at an upper portion of the manifold, the upper wall defining a capping surface at a first end of the bore along the longitudinal axis; a first supply line configured to supply an inactive purge gas to the bore at a first location along the longitudinal axis downstream of the capping surface; a second supply line configured to supply a gas to the bore at a second location along the longitudinal axis, the second location different from the first location.

17 . The semiconductor processing device of claim 16 , wherein the supply line is connected to an inactive gas source to purge the bore.

18 . The semiconductor processing device of claim 16 , wherein the inactive gas comprises at least one of argon gas and nitrogen gas.

19 . A method of deposition, the method comprising:
supplying a first gas through a first supply channel to a bore of a manifold at a first location along a longitudinal axis of the bore, a capping surface disposed at an upper end of the bore; supplying a second gas through a second supply channel to the bore of the manifold at a second location along the longitudinal axis of the bore that is longitudinally offset from the first supply channel; directing at least one of the first gas and the second gas downstream along the longitudinal axis towards an outlet of the bore.

20 . The method of claim 19 , wherein supplying the first and second gases comprises supplying a first vaporized reactant and supplying a second vaporized reactant.

21 . The method of claim 20 , further comprising purging the reaction chamber with an inactive gas after supplying the first vaporized reactant and before supplying the second vaporized reactant.

22 . The method of claim 21 , wherein the inactive gas comprises at least one of nitrogen gas and argon gas.

23 . The method of claim 22 , wherein the first vaporized reactant comprises at least one of H 2 , NH 3 , N 2 , O 2 , or O.

24 . The method of claim 23 , wherein the second vaporized reactant comprises at least one of dichlorosilane (DCS), trichlorosilane (TCS), trisilane, organic silanes, titanium chloride (TiCl 4 ), ZrCl 4 , and HfCl 4 .

25 . The method of claim 24 , wherein the first vaporized reactant comprises NH 3 and the second vaporized reactant comprises TiCl 4 .

26 . The method of claim 25 , further comprising vaporizing liquid TiCl 4 to create the second vaporized reactant.

Assignees

• Asm Ip Holding Bv

Inventors

• Nandwana Dinkar
• Shero Eric James
• White Carl Louis
• Dunn Todd Robert
• Petro William George
• Winkler Jereld Lee
• Chitale Aniket

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title

• H10P14/69394

  the material containing titanium, e.g. TiO2 · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title