Techniques to support multiple interconnect protocols for a common set of interconnect connectors

Patent metadata

Field	Value
Publication number	US-2021109300-A1
Application number	US-202016951723-A
Country	US
Kind code	A1
Filing date	Nov 18, 2020
Priority date	Jul 22, 2016
Publication date	Apr 15, 2021
Grant date	—

Abstract

Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

First claim

1 .- 25 . (canceled)

26 . An apparatus comprising:
a package including a plurality of integrated circuit dies, one or more of the plurality of integrated circuit dies including:
a memory controller to couple to a memory device;
a plurality of processing cores to execute instructions and process data;
a coherent interconnect fabric to couple the plurality of processing cores and the memory controller;
physical (PHY) interface circuitry comprising:
a plurality of connectors to couple the PHY interface circuitry to a plurality of data lanes, the plurality of connectors including a first subset of the connectors associated with a first interconnect protocol, a second subset of the connectors associated with a second interconnect protocol, and a third subset of the connectors associated with a third interconnect protocol;
a first sub-block including a first physical coding sub-layer (PCS) to encode data in accordance with the first interconnect protocol for communication over the first subset of connectors;
a second sub-block including a second PCS to encode data in accordance with the second interconnect protocol for communication over the second subset of connectors;
a third sub-block including a third PCS to encode data in accordance with the third interconnect protocol for communication over the third subset of connectors;

a multiplexer operable based on a physical or logical control input to connect the first subset of connectors to the first sub-block, to connect the second subset of the connectors to the second sub-block, and to connect the third subset of the connectors to the third sub-block;
first protocol layer circuitry to provide data received from the coherent interconnect fabric to the first sub-block and to provide data received from the first sub-block to the coherent interconnect fabric in accordance with the first interconnect protocol;
second protocol layer circuitry to provide data received from the coherent interconnect fabric to the second sub-block and to provide data received from the second sub-block to the coherent interconnect fabric in accordance with the second interconnect protocol; and
third protocol layer circuitry to provide data received from the coherent interconnect fabric to the third sub-block and to provide data received from the third sub-block to the coherent interconnect fabric in accordance with the third interconnect protocol.

27 . The apparatus of claim 26 wherein the physical or logical control input comprises a configuration signal received from a basic input-output system (BIOS) of a computer system.

28 . The apparatus of claim 26 wherein the physical or logical control input comprises a configuration signal based on a setting of one or more fuses.

29 . The apparatus of claim 26 wherein the physical or logical control input is generated based on a discovery operation performed by firmware and/or software of a computer system.

30 . The apparatus of claim 26 wherein the coherent interconnect fabric comprises a first agent to communicate with the first one or more protocol layer circuitry in accordance with the first interconnect protocol.

31 . The apparatus of claim 30 wherein the coherent interconnect fabric comprises a second agent to communicate with the second one or more protocol layer circuitry in accordance with the second interconnect protocol.

32 . The apparatus of claim 26 wherein the first interconnect protocol comprises a serial link protocol and the first subset of connectors are to perform serial input/output (TO) communication.

33 . The apparatus of claim 32 wherein the second interconnect protocol comprises a memory protocol and the second subset of connectors are coupled to a second serial interconnect supporting remote memory access.

34 . A method comprising:
providing a package including a plurality of integrated circuit dies, one or more of the plurality of integrated circuit dies including a memory controller to couple to a memory device, a plurality of processing cores to execute instructions and process data, and a coherent interconnect fabric to couple the plurality of processing cores and the memory controller; associating a first subset of connectors of a physical (PHY) interface circuit with a first interconnect protocol; associating a second subset of connectors of a physical (PHY) interface circuit with a second interconnect protocol; associating a third subset of connectors of a physical (PHY) interface circuit with a third interconnect protocol; connecting, via a multiplexer based on a physical or logical control input, a first sub-block including a first physical coding sub-layer (PCS) to the first subset of connectors, a second sub-block including a second PCS to the second subset of connectors, and a third sub-block including a third PCS to the third subset of connectors; encoding data by the first PCS, second PCS, and third PCS in accordance with the first, second, and third interconnect protocols, respectively, for communication over the first, second, and third subset of connectors, respectively; providing, by first protocol layer circuitry, data received from the coherent interconnect fabric to the first sub-block in accordance with the first interconnect protocol; providing, by the first protocol layer circuitry, data received from the first sub-block to the coherent interconnect fabric in accordance with the first interconnect protocol; providing, by second protocol layer circuitry, data received from the coherent interconnect fabric to the second sub-block in accordance with the second interconnect protocol; providing, by the second protocol layer circuitry, data received from the second sub-block to the coherent interconnect fabric in accordance with the second interconnect protocol; providing, by third protocol layer circuitry, data received from the coherent interconnect fabric to the third sub-block in accordance with the third interconnect protocol; and providing, by the third protocol layer circuitry, data received from the third sub-block to the coherent interconnect fabric in accordance with the third interconnect protocol.

35 . The method of claim 34 wherein the physical or logical control input comprises a configuration signal received from a basic input-output system (BIOS) of a computer system.

36 . The method of claim 34 wherein the physical or logical control input comprises a configuration signal based on a setting of one or more fuses.

37 . The method of claim 34 wherein the physical or logical control input is generated based on a discovery operation performed by firmware and/or software of a computer system.

38 . The method of claim 34 wherein the coherent interconnect fabric comprises a first agent to communicate with the first one or more protocol layer circuitry in accordance with the first interconnect protocol.

39 . The method of claim 38 wherein the coherent interconnect fabric comprises a second agent to communicate with the second one or more protocol layer circuitry in accordance with the second interconnect protocol.

40 . The method of claim 34 wherein the first interconnect protocol comprises a serial link protocol and the first subset of connectors are to perform serial input/output (IO) communication.

41 . The method of claim 40 wherein the second interconnect protocol comprises a memory protocol and the second subset of connectors are coupled to a second serial interconnect supporting remote memory access.

42 . A system comprising:
a system memory device; a package including a plural

Assignees

• Intel Corp

Inventors

• Wagh Mahesh
• Myers Mark S
• Van Doren Stephen R
• Ziakas Dimitrios
• Coury Bassam N

Classifications

• H04L45/02

  Topology update or discovery · CPC title

• H04L41/12

  Discovery or management of network topologies · CPC title

• G02B6/3897 Primary

  Connectors fixed to housings, casing, frames or circuit boards (G02B6/44528 takes precedence) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• H04L41/149

  for prediction of maintenance · CPC title