Method for Realizing a Neural Network

Patent metadata

Field	Value
Publication number	US-2021097388-A1
Application number	US-201816955356-A
Country	US
Kind code	A1
Filing date	Dec 12, 2018
Priority date	Dec 20, 2017
Publication date	Apr 1, 2021
Grant date	—

Abstract

A method for realizing an artificial neural network via an electronic integrated circuit (FPGA), wherein artificial neurons grouped into different interlinked layers for the artificial neural network, where a functional description is created for each neuron of the artificial neural network, taking into account a specifiable starting weighting, a synthesis is performed for each neuron based on the associated functional description with the associated specified starting weighting, a network list is determined as the synthesis result, in which at least a base element and a starting configuration belonging to the base element are stored for each neuron, a base element is formed as a lookup table (LUT) unit and an associated dynamic configuration cell, in which a current configuration for the LUT unit or the base element is stored, and where the network list is implemented as a starting configuration of the artificial neural network in the electronic integrated circuit.

First claim

1 .- 8 . (canceled)

9 . A method for realizing an artificial neural network via an electronic integrated circuit (SE), the artificial neural network being formed from artificial neurons which are grouped into different layers (ES, VS, AS) and linked to each other, the method comprising:
a. creating a functional description, taking into account a specifiable starting weighting for each neuron; b. performing a synthesis for each respective neuron based on a respective functional description with an associated specifiable starting weighting; c. creating a netlist as a synthesis result, at least one base element (BE 1 , BE 2 ) and a starting configuration belonging to the base element (BE 1 , BE 2 ) being stored in the netlist for each neuron, and the at least one base element (BE 1 , BE 2 ) being formed by a lookup table (LUT) unit (LUT 1 , LUT 2 ) and an associated dynamic configuration cell (KON 1 , KON 2 ), in which a respective current configuration for the associated LUT unit (LUT 1 , LUT 2 ) is stored ( 103 ); and d. implementing the netlist as a starting configuration of the neural network in the electronic integrated circuit (SE).

10 . The method as claimed in claim 9 , wherein, during the creation of the functional description, taking into account the specifiable starting weighting of the respective neuron, the functionality of the respective neuron is reduced such that the respective neuron is mapped onto one base element (BE 1 , BE 2 ).

11 . The method as claimed in claim 9 , wherein, starting from the starting configuration of the artificial neural network implemented in the electronic integrated circuit, a training phase of the artificial neural network is performed in which at least one of (i) the starting configuration and (ii) a respective current configuration of at least one of (i) at least one base element (BE 1 , BE 2 ) and (ii) at least one neuron is changed.

12 . The method as claimed in claim 10 , wherein, starting from the starting configuration of the artificial neural network implemented in the electronic integrated circuit, a training phase of the artificial neural network is performed in which at least one of (i) the starting configuration and (ii) a respective current configuration of at least one of (i) at least one base element (BE 1 , BE 2 ) and (ii) at least one neuron is changed.

13 . The method as claimed in claim 11 , wherein at least one of (i) fixed, specified test data and (ii) test samples are utilized in the training phase of the artificial neural network, output data obtained with at least one of (i) the test data and (ii) test sample is compared with specified reference data, and a change to the respective current configuration of at least one of (i) at least one base unit (BE 1 , BE 2 ) and (ii) at least one neuron is performed iteratively until the output data obtained with at least one of (i) the test data and (ii) the specified test sample corresponds to the specified reference data within a specifiable tolerance.

14 . The method as claimed in claim 11 , wherein a specially designated interface of the electronic integrated circuit (SE) is utilized during the training phase of the artificial neural network to feed in a change to at least one of (i) the starting configuration and (ii) the respective current configuration of at least one of (i) the at least one base unit (BE 1 , BE 2 ) and (ii) the neuron.

15 . The method as claimed in claim 13 , wherein a specially designated interface of the electronic integrated circuit (SE) is utilized during the training phase of the artificial neural network to feed in a change to at least one of (i) the starting configuration and (ii) the respective current configuration of at least one of (i) the at least one base unit (BE 1 , BE 2 ) and (ii) the neuron.

16 . The method as claimed in claim 9 , wherein a memory unit of a configuration memory of the electronic integrated circuit (SE) is utilized as the configuration cell (KON 1 , KON 2 ) for storing the respective current configuration of the respective base element.

17 . The method as claimed in claim 9 , wherein that the configuration cell (KON 1 , KON 2 ) for storing the respective current configuration of the respective base element comprises static RAM.

18 . The method as claimed in claim 9 , wherein the electronic integrated circuit (SE) comprises a Field Programmable Gate Array (FPGA).

19 . The method as claimed in claim 9 , wherein the functional description of the respective neuron is created in a hardware description language (HDL).

Assignees

• Siemens Ag

Inventors

• Hinterstoisser Thomas
• Matschnig Martin
• Taucher Herbert

Classifications

• G06N3/09

  Supervised learning · CPC title

• G06N3/0499

  Feedforward networks · CPC title

• G06F30/323

  Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06N3/063 Primary

  using electronic means · CPC title