Semiconductor package structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2021082783-A1
Application number	US-202017078422-A
Country	US
Kind code	A1
Filing date	Oct 23, 2020
Priority date	Aug 31, 2015
Publication date	Mar 18, 2021
Grant date	—

Abstract

A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die placed on the base substrate, the die including a semiconductor device, a solder bump placed on one surface of the die to exhaust heat generated in the die to an outside; and a solder ball placed on other surface of the die facing the one surface to transmit a signal, which is produced by the semiconductor device of the die, to an external device.

First claim

1 - 20 . (canceled)

21 . A semiconductor package structure, comprising:
a re-distribution substrate; a die mounted on the re-distribution substrate, the die including a joining pattern; a solder bump joined to the joining pattern on the die; a polymer resin layer embedding the die on the re-distribution substrate, the solder bump being exposed to an upper surface of the polymer resin layer; a base substrate on the polymer resin layer; a contact plug connecting the re-distribution substrate and the base substrate on a side of the die; and an upper package mounted on the base substrate and including an upper substrate and an upper die mounted on the upper substrate, wherein the base substrate includes a heat dissipation plug penetrating the base substrate, and wherein the solder bump connects the heat dissipation plug and the joining pattern to each other.

22 . The semiconductor package structure of claim 21 , wherein the base substrate includes a solder mask disposed on the base substrate, the solder mask defining an opening area that corresponds to the heat dissipation plug, and
wherein the solder bump disposed in the opening area between the heat dissipation plug and the die, and configured to discharge heat generated in the die to an outside.

23 . The semiconductor package structure of claim 22 , wherein the solder bump is coupled to the base substrate through the opening area.

24 . The semiconductor package structure of claim 21 , wherein a direction of heat, which is generated in the die and is discharged to the outside through the solder bump, and a direction of a signal, which is produced by a semiconductor device in the die and is transmitted to an external device, are anti-parallel to each other.

25 . The semiconductor package structure of claim 21 , wherein the solder bump comprises a first portion facing the die and a second portion facing the heat dissipation plug, and
wherein a width of the first portion is different than a width of the second portion.

26 . The semiconductor package structure of claim 23 , wherein the heat dissipation plug is provided in plural, and
wherein the solder bump is connected to two of the plurality of the heat dissipation plugs.

27 . The semiconductor package structure of claim 21 , wherein the joining pattern provides an interface between the die and the solder bump, and wherein the joining pattern is electrically disconnected from the die.

28 . The semiconductor package structure of claim 21 , wherein the base substrate has a plate shape, and
wherein the polymer resin layer surrounds the contact plug.

29 . The semiconductor package structure of claim 21 , further comprising a solder ball disposed on a bottom surface of the base substrate, opposite to the die, and configured to transmit a signal, which is produced by a semiconductor device of the die, to an external device.

30 . A semiconductor package structure, comprising:
a base substrate including heat dissipation plugs penetrating the base substrate; a solder mask disposed on the base substrate, the solder mask defining an opening area that corresponds to at least two of the heat dissipation plugs; a die disposed on the base substrate, the heat dissipation plugs being configured to discharge heat generated in the die to an outside; a solder bump that is interposed between the die and the opening area, the solder bump being coupled to the base substrate through the opening area; a re-distribution layer disposed on the die, the die being mounted at the re-distribution layer; a contact plug connecting the re-distribution layer and the base substrate on a side of the die; and a solder ball disposed on the re-distribution layer and configured to transmit a signal, which is produced by a semiconductor device of the die, to an external device, wherein the solder bump is connected to two of the plurality of the heat dissipation plugs.

31 . The semiconductor package structure of claim 30 , a joining pattern that is interposed between the die and the solder bump,
wherein the solder bump connects one of the heat dissipation plugs and the joining pattern to each other.

32 . The semiconductor package structure of claim 31 , wherein the joining pattern is electrically disconnected from the die.

33 . The semiconductor package structure of claim 30 , wherein a direction of the heat, which is generated in the die and is discharged to the outside through the solder bump, and a direction of the signal, which is produced by the semiconductor device in the die and is transmitted to the external device through the solder ball, are anti-parallel to each other.

34 . The semiconductor package structure of claim 30 , wherein the solder bump comprises a first portion facing the die and a second portion facing the heat dissipation plugs, and
wherein a width of the first portion is different than a width of the second portion.

35 . The semiconductor package structure of claim 30 , further comprising a polymer resin layer embedding the die on the re-distribution layer, the solder bump being exposed to an upper surface of the polymer resin layer,
wherein the base substrate has a plate shape, and wherein the polymer resin layer surrounds the contact plug.

36 . The semiconductor package structure of claim 30 , further comprising a polymer resin layer embedding the die on the re-distribution layer, the solder bump being exposed to an upper surface of the polymer resin layer,
wherein the polymer resin layer and the die is disposed in a cavity of the base substrate, and wherein the contact plug disposed in the base substrate.

37 . A semiconductor package structure, comprising:
a base substrate; a die disposed in a cavity of the base substrate; a polymer resin layer filling in the cavity; a re-distribution layer disposed on the base substrate, the die being mounted at the re-distribution layer; a solder bump between a bottom surface of the cavity and the die, the solder bump being joined to the die by a joining pattern; a solder mask disposed on the bottom surface of the cavity, the solder mask defining an opening area that corresponds to the solder bump, and a solder ball disposed on the re-distribution layer and configured to transmit a signal, which is produced by a semiconductor device of the die, to an external device, wherein the solder bump comprises:
a heat dissipation plug penetrating the base substrate under the cavity; and
a contact plug connecting the re-distribution layer and the base substrate on a side of the cavity, and
wherein the solder bump is coupled to the heat dissipation plug through the opening area.

38 . The semiconductor package structure of claim 37 , wherein the joining pattern is electrically disconnected from the die.

39 . The semiconductor package structure of claim 37 , wherein the solder bump comprises a first portion facing the die and a second portion facing the heat dissipation plug, and
wherein a width of the first portion is different than a width of the second portion.

40 . The semiconductor package structure of claim 37 , wherein a direction of heat, which is generated in the die and is discharged to the outside through the solder bump, and a direction of the signal, which is produced by the semiconductor device in the die and is transmitted to the external device through the solder ball, are anti-parallel to each other.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Youngho
• Park Hwanpil

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title