Logarithmic Power Detector

Patent metadata

Field	Value
Publication number	US-2021067108-A1
Application number	US-202016990967-A
Country	US
Kind code	A1
Filing date	Aug 11, 2020
Priority date	Aug 30, 2019
Publication date	Mar 4, 2021
Grant date	—

Abstract

A logarithmic power detector includes a power distributor, a first detection circuit, a second detection circuit and an output circuit. The power distributor is used to generate a first power signal and a second power signal according to an input signal. The first detection circuit is used to attenuate the first power signal to generate a first rectified signal, filter the first rectified signal to generate a first low-pass signal, and amplify the first low-pass signal to generate a first amplification current. The second detection circuit is used to attenuate the second power signal to generate a second rectified signal, filter the second rectified signal to generate a second low-pass signal, and amplify the second low-pass signal to generate a second amplification current. The output circuit is used to receive the first amplification current and the second amplification current to generate a converted voltage related to the input signal.

First claim

What is claimed is:

1 . A logarithmic power detector comprising:
an input terminal configured to receive an input signal; a power distributor coupled to the input terminal and configured to generate a first power signal and a second power signal according to the input signal; a first detecting circuit coupled to the power distributor and comprising:
a first half-wave rectifier coupled to the power distributor and configured to attenuate half cycles of the first power signal to generate a first rectified signal;
a first low-pass filter coupled to the first half-wave rectifier and configured to pass the first rectified signal to generate a first low-pass signal; and
a first buffer coupled to the first low-pass filter and configured to amplify the first low-pass signal to generate a first amplified current;
a second detecting circuit coupled to the power distributor and comprising:
a second half-wave rectifier coupled to the power distributor and configured to attenuate half cycles of the second power signal to generate a second rectified signal;
a second low-pass filter coupled to the second half-wave rectifier and configured to pass the second rectified signal to generate a second low-pass signal; and
a second buffer coupled to the second low-pass filter and configured to amplify the second low-pass signal to generate a second amplified current; and
an output circuit coupled to the first buffer and the second buffer and configured to receive the first amplified current and the second amplified current to generate a converted voltage; wherein the converted voltage is related to power of the input signal.

2 . The logarithmic power detector of claim 1 , wherein the power distributor comprises:
a first impedance unit coupled to the first half-wave rectifier and the input terminal and configured to generate the first power signal according to the input signal; and a second impedance unit coupled to the second half-wave rectifier and the input terminal and configured to generate the second power signal according to the input signal.

3 . The logarithmic power detector of claim 2 , wherein the first impedance unit comprises a capacitor, a resistor or a coupler, and the second impedance unit comprises a capacitor, a resistor or a coupler.

4 . The logarithmic power detector of claim 1 , wherein the power distributor comprises:
a first impedance unit configured to generate the first power signal according to the input signal and comprising a first terminal coupled to the input terminal and a second terminal coupled to the first half-wave rectifier; and a second impedance unit configured to generate the second power signal according to the input signal and comprising a first terminal coupled to the first half-wave rectifier and a second terminal coupled to the second half-wave rectifier.

5 . The logarithmic power detector of claim 4 , wherein the first impedance unit comprises a capacitor, a resistor or a coupler, and the second impedance unit comprises a capacitor, a resistor or a coupler.

6 . The logarithmic power detector of claim 1 , wherein the half cycles are positive half cycles.

7 . The logarithmic power detector of claim 1 , wherein:
the first half-wave rectifier comprises a first diode comprising:
an anode coupled to the power distributor and the first low-pass filter; and
a cathode coupled to a reference voltage terminal; and
the second half-wave rectifier comprises a second diode comprising:
an anode coupled to the power distributor and the second low-pass filter; and
a cathode coupled to the reference voltage terminal.

8 . The logarithmic power detector of claim 7 , wherein:
the first half-wave rectifier further comprises a third diode comprising:
an anode coupled to the anode of the first diode and the first low-pass filter; and
a cathode coupled to the power distributor; and
the second half-wave rectifier further comprises a fourth diode comprising:
an anode coupled to the anode of the second diode and the second low-pass filter; and
a cathode coupled to the power distributor.

9 . The logarithmic power detector of claim 1 , wherein:
the first half-wave rectifier comprises a first transistor comprising:
a control terminal;
a first terminal coupled to the power distributor, the first low-pass filter and the control terminal of the first transistor; and
a second terminal coupled to a reference voltage terminal; and
the second half-wave rectifier comprises a second transistor comprising:
a control terminal;
a first terminal coupled to the power distributor, the second low-pass filter and the control terminal of the second transistor; and
a second terminal coupled to the reference voltage terminal.

10 . The logarithmic power detector of claim 9 , wherein:
the first half-wave rectifier further comprises a first resistor coupled between the first terminal of the first transistor and the control terminal of the first transistor; and the second half-wave rectifier further comprises a second resistor coupled between the first terminal of the second transistor and the control terminal of the second transistor.

11 . The logarithmic power detector of claim 9 , wherein:
the first half-wave rectifier comprises a third transistor comprising:
a control terminal;
a first terminal coupled to the power distributor; and
a second terminal coupled to the first terminal of the first transistor, the first low-pass filter and the control terminal of the third transistor; and
the second half-wave rectifier comprises a fourth transistor comprising:
a control terminal;
a first terminal coupled to the power distributor; and
a second terminal coupled to the first terminal of the second transistor, the second low-pass filter and the control terminal of the fourth transistor.

12 . The logarithmic power detector of claim 1 , wherein:
the first low-pass filter comprising:
a third resistor comprising a first terminal coupled to the first half-wave rectifier and a second terminal coupled to the first buffer; and
a first capacitor comprising a first terminal coupled to the first buffer and the second terminal of the third resistor and a second terminal coupled to a reference voltage terminal; and
the second low-pass filter comprising:
a fourth resistor comprising a first terminal coupled to the second half-wave rectifier and a second terminal coupled to the second buffer; and
a second capacitor comprising a first terminal coupled to the second buffer and the second terminal of the fourth resistor and a second terminal coupled to the reference voltage terminal.

13 . The logarithmic power detector of claim 1 , wherein the first buffer comprises a first amplifier, and the second buffer comprises a second amplifier.

14 . The logarithmic power detector of claim 13 , wherein the first amplifier and the second amplifier are inverting amplifiers.

15 . The logarithmic power detector of claim 1 , wherein the output circuit comprises a third buffer coupled to the first buffer and the second buffer and configured to receive the first amplified current and the second amplified current to generate the converted voltage.

16 . The logarithmic power detector of claim 1 , wherein the output circuit comprises an adder comprising:
an operational amplifier comprising a non-inverting input terminal, an inverting input terminal and an output terminal; a first adder resistor comprising a first terminal coupled to the first buffer and a second terminal coupled to the non-inverting input terminal of the operational amplifier; a

Assignees

• Richwave Technology Corp

Inventors

• Chien Hwey-Ching
• Tai Chun-Han

Classifications

• H03F1/32 Primary

  Modifications of amplifiers to reduce non-linear distortion (by negative feedback H03F1/34) · CPC title

• H03F1/42

  Modifications of amplifiers to extend the bandwidth · CPC title

• H04B17/101

  for measurement of specific parameters of the transmitter or components thereof · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03F2200/504

  the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier · CPC title