Integrated circuit devices with capacitors

Patent metadata

Field	Value
Publication number	US-2021066214-A1
Application number	US-201916552551-A
Country	US
Kind code	A1
Filing date	Aug 27, 2019
Priority date	Aug 27, 2019
Publication date	Mar 4, 2021
Grant date	—

Abstract

An integrated circuit device is provided. In some examples, an integrated circuit die of the device includes a first capacitor arranged such that when the integrated circuit die is coupled to a package, the package affects a capacitance of the first capacitor, a second capacitor disposed directly underneath the first capacitor, and a capacitance measurement circuit coupled to the first capacitor and the second capacitor to determine the capacitance of the first capacitor and a capacitance of the second capacitor. The integrated circuit device may detect tampering with the die and/or the package based on the capacitances of the first capacitor and the second capacitor.

First claim

What is claimed is:

1 . An integrated circuit die comprising:
a first capacitor arranged such that when the integrated circuit die is coupled to a package, the package affects a capacitance of the first capacitor; a second capacitor disposed directly underneath the first capacitor; and a capacitance measurement circuit coupled to the first capacitor and the second capacitor to determine the capacitance of the first capacitor and a capacitance of the second capacitor.

2 . The integrated circuit die of claim 1 further comprising a multilayer interconnect, wherein the first capacitor includes:
a first capacitor plate disposed in a first layer of the multilayer interconnect; and
a second capacitor plate disposed in the first layer of the multilayer interconnect that surrounds the first capacitor plate.

3 . The integrated circuit die of claim 2 further comprising a set of conductive shield features disposed between the first capacitor and the second capacitor in a second layer of the multilayer interconnect.

4 . The integrated circuit die of claim 2 , wherein the second capacitor includes:
a first capacitor plate that includes conductive features in a second layer of the multilayer interconnect; and a second capacitor plate that includes conductive features in the second layer that surround the conductive features of the first capacitor plate.

5 . The integrated circuit die of claim 4 , wherein:
the first capacitor plate of the second capacitor further includes conductive features in a third layer of the multilayer interconnect; and the second capacitor plate of the second capacitor further includes conductive features in the third layer.

6 . The integrated circuit die of claim 1 further comprising:
a substrate disposed below the second capacitor; and
a set of conductive shield features disposed between the second capacitor and the substrate.

7 . The integrated circuit die of claim 1 , wherein the capacitance measurement circuit is to provide a ratio of the capacitance of the first capacitor to the capacitance of the second capacitor.

8 . The integrated circuit die of claim 7 further comprising an encryption control circuit coupled to the capacitance measurement circuit to receive the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor.

9 . The integrated circuit die of claim 8 , wherein the encryption control circuit is to detect tampering based on the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor.

10 . The integrated circuit die of claim 8 , wherein the encryption control circuit is to attempt to decrypt an encryption key based on the ratio.

11 . The integrated circuit die of claim 8 , wherein the encryption control circuit is to delete an encryption key based on the ratio.

12 . An integrated circuit comprising:
a die that includes:
a first capacitor;
a second capacitor disposed proximate to the first capacitor;
a capacitance measurement circuit coupled to the first capacitor and the second capacitor to determine a capacitance of the first capacitor and a capacitance of the second capacitor; and
a circuit to determine tampering of the integrated circuit based on the capacitance of the first capacitor and the capacitance of the second capacitor.

13 . The integrated circuit of claim 12 , wherein:
the integrated circuit includes a package coupled to the die and arranged such that the package affects the capacitance of the first capacitor; and the tampering is with respect to the package and changes the capacitance of the first capacitor.

14 . The integrated circuit of claim 12 , wherein:
the die includes a substrate disposed below the first capacitor and arranged such that the substrate affects the capacitance of the first capacitor; and the tampering is with respect to the substrate and changes the capacitance of the first capacitor.

15 . The integrated circuit of claim 12 , wherein the second capacitor is disposed such that, when the capacitance of the first capacitor is affected by the tampering, the capacitance of the second capacitor is unaffected by the tampering.

16 . The integrated circuit of claim 12 , wherein the circuit is to determine the tampering based on a change in a ratio of the capacitance of the first capacitor to the capacitance of the second capacitor.

17 . A computing system comprising:
a processing resource; a non-transitory computer-readable medium coupled to the processing resource and storing instructions that, when executed by the processing resource, cause the processing resource to:
receive a capacitance of a first capacitor of a die;
receive a capacitance of a second capacitor of the die; and
detect tampering based on a ratio of the capacitance of the first capacitor to the capacitance of the second capacitor.

18 . The computing system of claim 17 , wherein:
the capacitance of the first capacitor is a first capacitance of the first capacitor and is received during a qualification process; the capacitance of the second capacitor is a first capacitance of the second capacitor and is received during the qualification process; and the non-transitory computer-readable medium stores further instructions that cause the processing resource to:
encrypt an encryption key based on the ratio of the first capacitance of the first capacitor to the first capacitance of the second capacitor;
receive a second capacitance of the first capacitor;
receive a second capacitance of the second capacitor;
attempt to decrypt the encryption key based on a ratio of the second capacitance of the first capacitor to the second capacitance of the second capacitor; and
detect the tampering based on a failure to decrypt the encryption key.

19 . The computing system of claim 17 , wherein the non-transitory computer-readable medium stores further instructions that cause the processing resource to delete an encryption key based on the tampering.

20 . The computing system of claim 17 , wherein the tampering is with respect to an element from a group consisting of: a package coupled to the die and a substrate of the die.

Assignees

• Texas Instruments Inc

Inventors

• Das Abhijit Kumar
• Bellary Suman
• Bittlestone Clive

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/423

  Shielding layers · CPC title

• H10W42/405

  using active circuits · CPC title

• H10W42/40 Primary

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• G06F21/86 Primary

  Secure or tamper-resistant housings · CPC title