Methods of fabricating semiconductor package

Patent metadata

Field	Value
Publication number	US-2021066149-A1
Application number	US-202016866594-A
Country	US
Kind code	A1
Filing date	May 5, 2020
Priority date	Aug 30, 2019
Publication date	Mar 4, 2021
Grant date	—

Abstract

Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor package, the method comprising:
forming a first barrier layer on a first carrier; forming a sacrificial layer on the first barrier layer, the sacrificial layer including an opening that exposes at least a portion of the first barrier layer; forming a second barrier layer on the first barrier layer and on the sacrificial layer, the second barrier layer including a portion formed on the sacrificial layer; forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer; forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer; mounting a semiconductor chip on the redistribution structure; attaching a second carrier onto the semiconductor chip and removing the first carrier; removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure; and forming solder balls, respectively, on the portions of the redistribution structure.

2 . The method of claim 1 , wherein the sacrificial layer and the redistribution layer include the same material.

3 . The method of claim 1 , wherein the sacrificial layer includes a metallic material.

4 . The method of claim 3 , wherein the metallic material includes copper.

5 . The method of claim 1 , wherein the first and second barrier layers include a different material from the sacrificial layer.

6 . The method of claim 1 , wherein removing the first barrier layer, the sacrificial layer, and the second barrier layer includes performing a wet etching process.

7 . The method of claim 1 , wherein the second insulating layer extends on a side of the redistribution layer, and
wherein the first and second insulating layers include a photo-imageable dielectric material.

8 . The method of claim 1 , wherein removing the first barrier layer, the sacrificial layer, and the second barrier layer comprises forming trenches in the first insulating layer.

9 . The method of claim 8 , wherein forming the solder balls comprises forming the solder balls in the trenches, respectively.

10 . The method of claim 9 , wherein the trenches expose portions of the redistribution layer, respectively, and the solder balls contact, respectively, the portions of the redistribution layer.

11 . A method of fabricating a semiconductor package, the method comprising:
sequentially forming a release layer and a first barrier layer on a first carrier; forming a sacrificial layer on the first barrier layer, the sacrificial layer including a metallic material and an opening that exposes at least a portion of the first barrier layer; forming a second barrier layer extending on the first barrier layer and on the sacrificial layer; forming a first insulating layer that is thicker than the sacrificial layer in the opening; forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer; mounting a semiconductor chip on the redistribution structure; attaching a second carrier onto the semiconductor chip and removing the first carrier and the release layer; removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution layer; and forming solder balls, respectively, on the portions of the redistribution layer.

12 . The method of claim 11 , wherein the metallic material includes copper.

13 . The method of claim 11 , wherein the first insulating layer comprises a first bottom surface facing the first barrier layer and a first top surface opposite the first bottom surface, and the second barrier layer comprises a second bottom surface facing the first barrier layer and a second top surface opposite the second bottom surface, and
the first top surface of the first insulating layer is farther from the first barrier layer than the second top surface of the second barrier layer.

14 . The method of claim 11 , wherein the first and second barrier layers include a different material from the sacrificial layer.

15 . The method of claim 11 , wherein removing the first barrier layer, the sacrificial layer, and the second barrier layer comprises sequentially removing the first barrier layer, the sacrificial layer, and the second barrier layer by performing an etching process.

16 . The method of claim 11 , wherein the release layer includes the same material as the first insulating layer.

17 . A method of fabricating a semiconductor package, the method comprising:
sequentially forming a release layer and a first barrier layer on a first carrier; forming a sacrificial layer on the first barrier layer, the sacrificial layer including an opening that exposes at least a portion of the first barrier layer; forming a second barrier layer conformally on the first barrier layer and on the sacrificial layer; forming a first insulating layer in the opening, a top surface of the first insulating layer being farther from the first barrier layer than a top surface of a portion of the second barrier layer formed on the sacrificial layer; forming a redistribution structure on the first insulating layer and on the second barrier layer, the redistribution structure including a redistribution layer and a second insulating layer that is stacked on the redistribution layer to surround the redistribution layer; mounting a semiconductor chip on the redistribution structure; attaching a second carrier onto the semiconductor chip and removing the first carrier; removing the release layer; sequentially removing the first barrier layer, the sacrificial layer, and the second barrier layer; and forming a solder ball in a space from which the sacrificial layer has been removed, the solder ball being electrically connected to the redistribution layer.

18 . The method of claim 17 , further comprising:
forming a molding part covering at least a portion of the semiconductor chip and the redistribution structure.

19 . The method of claim 18 , wherein a top surface of the molding part is coplanar with a top surface of the semiconductor chip.

20 . The method of claim 17 , wherein sequentially removing the first barrier layer, the sacrificial layer, and the second barrier layer comprises performing a wet etching process.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jung-Ho
• Park Jin-Woo
• Jang Jae Gwon
• Jeon Gwang Jae

Classifications

• H10P72/7448

  the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/07236

  Soldering or alloying · CPC title