Power Semiconductor Package and Method for Fabricating a Power Semiconductor Package

Patent metadata

Field	Value
Publication number	US-2021057375-A1
Application number	US-202016991123-A
Country	US
Kind code	A1
Filing date	Aug 12, 2020
Priority date	Aug 20, 2019
Publication date	Feb 25, 2021
Grant date	—

Abstract

A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

First claim

What is claimed is:

1 . A power semiconductor package, comprising:
a power semiconductor chip; an electrical connector arranged at a first side of the power semiconductor chip and comprising a first surface that is coupled to a power electrode of the power semiconductor chip; an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector; and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

2 . The power semiconductor package of claim 1 , wherein the encapsulation body and the electrical insulation layer comprise grinding traces at the coplanar surface of the semiconductor package.

3 . The power semiconductor package of claim 1 , wherein the electrical insulation layer comprises a thermal interface material, and wherein the coplanar surface is configured to be coupled to a heatsink.

4 . The power semiconductor package of claim 1 , further comprising:
a die carrier, wherein the power semiconductor chip is arranged on the die carrier, and wherein the die carrier is exposed from the encapsulation body at a side of the power semiconductor package opposite to the coplanar surface.

5 . The power semiconductor package of claim 1 , wherein the parts of the encapsulation body of the coplanar surface are contaminated with grinding particles of the insulation layer material.

6 . The power semiconductor package of claim 1 , wherein the insulation layer is contaminated with grinding particles of encapsulation body material.

7 . The power semiconductor package of claim 1 , wherein the electrical connector comprises a metal clip.

8 . A method for fabricating a power semiconductor package, the method comprising:
providing a power semiconductor chip; arranging an electrical connector at a first side of the power semiconductor chip and coupling a first surface of the electrical connector to a power electrode on the first side of the power semiconductor chip; arranging an electrical insulation layer at a second surface of the electrical connector opposite the first surface; encapsulating the power semiconductor chip and the electrical connector at least partially with an encapsulation body; and thinning the encapsulation body and the electrical insulation layer such that after the thinning parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

9 . The method of claim 8 , wherein the thinning comprises one of a grinding, etching, sawing and ablation process or a combination thereof.

10 . The method of claim 8 , wherein the electrical insulation layer is arranged at the second surface of the electrical connector using a printing process or by depositing a preform.

11 . The method of claim 8 , further comprising:
curing the electrical insulation layer prior to encapsulating with the encapsulation body.

12 . The method of claim 8 , wherein the encapsulating comprises a molding process.

13 . The method of claim 8 , further comprising:
after the thinning, arranging a heatsink at the coplanar surface.

14 . A method for fabricating a power semiconductor package, the method comprising:
providing a power semiconductor chip; arranging an electrical connector over the power semiconductor chip and coupling a first surface of the electrical connector to a power electrode of the power semiconductor chip; encapsulating the power semiconductor chip and the electrical connector at least partially with an encapsulation body such that a second surface of the electrical connector, opposite the first surface, is at least partially exposed; and arranging an electrical insulation layer over the exposed part of the electrical connector such that parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

15 . The method of claim 14 , wherein the electrical insulation layer is arranged over the exposed part of the electrical connector using a printing process or by depositing a preform.

16 . The method of claim 14 , wherein the encapsulating comprises a molding process.

17 . The method of claim 14 , further comprising:
curing the electrical insulation layer.

Assignees

• Infineon Technologies Ag

Inventors

• Lim Wee Aun Jason
• Calo Paul Armand Asentista
• Chin Ting Soon
• Chong Chooi Mei
• Murugan Sanjay Kumar
• Sam Ying Pok
• Tan Chee Voon

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/767

  between a chip and a laterally-adjacent lead frame, conducting package substrate or heat sink · CPC title

• H10W72/07636

  Soldering or alloying · CPC title

• H10W72/07631

  Techniques · CPC title

• H10W72/01615

  Forming coatings · CPC title