Integrated chip and manufacturing method therefor, and full-color integrated chip and display panel
US-12183868-B2 · Dec 31, 2024 · US
US2021050480A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2021050480-A1 |
| Application number | US-202016907650-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 22, 2020 |
| Priority date | Sep 18, 2009 |
| Publication date | Feb 18, 2021 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
High-performance light-emitting diode together with apparatus and method embodiments thereto are disclosed. The light emitting diode devices emit at a wavelength of 390 nm to 470 nm or at a wavelength of 405 nm to 430 nm. Light emitting diode devices are characterized by having a geometric relationship (e.g., aspect ratio) between a lateral dimension of the device and a vertical dimension of the device such that the geometric aspect ratio forms a volumetric light emitting diode that delivers a substantially flat current density across the device (e.g., as measured across a lateral dimension of the active region). The light emitting diode devices are characterized by having a current density in the active region of greater than about 175 Amps/cm2.
Opening claim text (preview).
What is claimed is: 1 . An electrical or opto-electrical subassembly comprising: A submount defining at least a first contact; a chip mounted on said submount defining at least a second contact, wherein said first and second contacts define a distance therebetween; wherein at least one of said first or second contacts defines a coated portion comprising a layer of material having low wettability for solder, and a non-coated portion; and solder electrically connecting said first and second contacts, said solder being balled-up on said non-coated portion to span said distance between said first and second contacts.
Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title
of interconnections · CPC title
of packages · CPC title
Containers · CPC title
Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.