Array substrate, method for fabricating the same, display panel, and display device

Patent metadata

Field	Value
Publication number	US-2021028200-A1
Application number	US-201816332882-A
Country	US
Kind code	A1
Filing date	Sep 21, 2018
Priority date	Dec 6, 2017
Publication date	Jan 28, 2021
Grant date	—

Abstract

This disclosure provides an array substrate, a method for fabricating the same, a display panel, and a display device, where a first photo-resist layer is stripped in a changed order in that the first photo-resist layer on a source-drain is stripped through wet etching before a ohm contact layer film and an active layer film are etched in an electrically-conductive channel area (i.e., an electrically-conductive channel of a TFT is etched) to form an ohm contact layer and an active layer.

First claim

1 . A method for fabricating an array substrate, the method comprising:
forming a gate, a gate insulation layer, an active layer film, an ohm contact layer film, and a Cu layer on a base successively; forming a first photo-resist layer on the Cu layer, and patterning the first photo-resist layer to form a first photo-resist pattern; etching the Cu layer, the ohm contact layer film, and the active layer film using the first photo-resist pattern to form a source-drain at the Cu layer, and to remove patterns other than patterns corresponding to the source-drain and an electrically-conductive channel area, at the ohm contact layer film and the active layer film; stripping the first photo-resist layer through a wet etching; forming a pixel electrode in partial contact with the source-drain from which the first photo-resist layer is stripped, on the source-drain; and etching the ohm contact layer film and the active layer film in the electrically-conductive channel area by using the source-drain as a shelter, to form an ohm contact layer and an active layer.

2 . The method according to claim 1 , wherein the etching the Cu layer, the ohm contact layer film, and the active layer film using the first photo-resist pattern comprises:
performing a first wet etching on the Cu layer by using the first photo-resist pattern as a shelter, to remove the pattern other than patterns corresponding to the source-drain and the electrically-conductive channel area, at the Cu layer; performing a first dry etching on the ohm contact layer film and the active layer film by using the first photo-resist pattern as a shelter, to remove the patterns other than patterns corresponding to the source-drain and the electrically-conductive channel area, at the ohm contact layer film and the active layer film; thinning the first photo-resist pattern to remove the first photo-resist pattern in the electrically-conductive channel area; and performing a second wet etching on the Cu layer by using thinned first photo-resist pattern as a shelter, to remove the pattern of the Cu layer corresponding to the electrically-conductive channel area to form the source-drain.

3 . The method according to claim 2 , wherein the etching the ohm contact layer film and the active layer film in the electrically-conductive channel area comprises:
performing a second dry etching on the ohm contact layer film and the active layer film to remove the patterns other than patterns corresponding to the electrically-conductive channel area, at the ohm contact layer film and the active layer film.

4 . The method according to claim 1 , wherein the forming the pixel electrode in partial contact with the source-drain from which the first photo-resist layer is stripped, on the source-drain comprises:
forming a transparent electrode layer on the source-drain from which the first photo-resist layer is striped; forming a second photo-resist layer on the transparent electrode layer, and patterning the second photo-resist layer to form a second photo-resist pattern; etching the transparent electrode layer using the second photo-resist layer to form a pixel electrode; and stripping the second photo-resist layer on the pixel electrode.

5 . The method according to claim 1 , wherein after the ohm contact layer and the active layer are formed, the method further comprises:
forming a passivation layer on the pixel electrode.

6 . The method according to claim 5 , further comprises:
forming a common electrode on the passivation layer.

7 . The method according to claim 1 , wherein before the gate is formed, the method further comprises:
forming a common electrode on the base substrate.

8 . An array substrate fabricated using the method according to claim 1 , the array substrate comprising:
a base substrate; a gate on the base substrate; a gate insulation layer covering the gate, on the base substrate; an active layer on the gate insulation layer; an ohm contact layer on the active layer; a source-drain on the ohm contact layer, and made of Cu; and a pixel electrode on the source-drain, and in partially contact with the source-drain.

9 . The array substrate according to claim 8 , further comprises: a passivation layer on the pixel electrode.

10 . The array substrate according to claim 9 , further comprises: a common electrode on the passivation layer.

11 . The array substrate according to claim 9 , further comprises: a common electrode at a layer same as a layer at which the gate is.

12 . A display panel, comprising the array substrate according to claim 8 .

13 . A display device, comprising the display panel according to claim 12 .

14 . The display panel according to claim 12 , further comprises: a passivation layer on the pixel electrode.

15 . The display panel according to claim 14 , further comprises: a common electrode on the passivation layer.

16 . The display panel according to claim 14 , further comprises: a common electrode at a layer same as a layer at which the gate is.

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Han Xiao
• Bai Jinchao
• Ding Xiangqian
• Guo Huibin

Classifications

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title