Auto-referenced memory cell read techniques

Patent metadata

Field	Value
Publication number	US-2021020239-A1
Application number	US-202017062127-A
Country	US
Kind code	A1
Filing date	Oct 2, 2020
Priority date	Dec 22, 2017
Publication date	Jan 21, 2021
Grant date	—

Abstract

Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

First claim

What is claimed is:

1 . A method, comprising:
receiving, at a controller, a first set of bits of an input vector from a host device; allocating a block of memory to store the first set of bits of the input vector and a second set of bits based at least in part on a total number bits of the first set of bits; generating the second set of bits based at least in part on a number of bits of the first set of bits having a first logic state; and writing the first set of bits and the second set of bits at the block of memory.

2 . The method of claim 1 , wherein:
the second set of bits comprises multiple couples of bits representative of the number of bits of the first set of bits having the first logic state.

3 . The method of claim 1 , wherein generating the second set of bits comprises:
determining the number of bits of the first set of bits having the first logic state; and generating a set of bit values corresponding to the determined number of bits.

4 . The method of claim 1 , wherein:
the first logic state is associated with a logic state of 1.

5 . The method of claim 1 , wherein:
the first logic state is associated with a logic state corresponding to a first set of threshold voltages.

6 . The method of claim 5 , wherein:
the first set of threshold voltages are threshold voltages less than threshold voltages of a second set of threshold voltages associated with a second logic state.

7 . The method of claim 7 , wherein:
the second logic state is associated with a logic state of 0.

8 . An apparatus, comprising:
a block of memory; and a controller coupled with the block of memory and operable to cause the apparatus to:
receive a first set of bits of an input vector from a host device;
allocate the block of memory to store the first set of bits of the input vector and a second set of bits based at least in part on a total number bits of the first set of bits;
generate the second set of bits based at least in part on a number of bits of the first set of bits having a first logic state; and
write the first set of bits and the second set of bits at the block of memory.

9 . The apparatus of claim 8 , wherein:
the second set of bits comprises multiple couples of bits representative of the number of bits of the first set of bits having the first logic state.

10 . The apparatus of claim 8 , wherein the controller is further operable to cause the apparatus to:
determine the number of bits of the first set of bits having the first logic state; and generate a set of bit values corresponding to the determined number of bits.

11 . The apparatus of claim 8 , wherein:
the first logic state is associated with a logic state of 1.

12 . The apparatus of claim 8 , wherein:
the first logic state is associated with a logic state corresponding to a first set of threshold voltages.

13 . The apparatus of claim 12 , wherein:
the first set of threshold voltages are threshold voltages less than threshold voltages of a second set of threshold voltages associated with a second logic state.

14 . The apparatus of claim 13 , wherein:
the second logic state is associated with a logic state of 0.

15 . An apparatus, comprising:
means for receiving, at a controller, a first set of bits of an input vector from a host device; means for allocating a block of memory to store the first set of bits of the input vector and a second set of bits based at least in part on a total number bits of the first set of bits; means for generating the second set of bits based at least in part on a number of bits of the first set of bits having a first logic state; and means for writing the first set of bits and the second set of bits at the block of memory.

16 . The apparatus of claim 15 , wherein:
the second set of bits comprises multiple couples of bits representative of the number of bits of the first set of bits having the first logic state.

17 . The apparatus of claim 15 , wherein the means for generating the second set of bits comprises:
means for determining the number of bits of the first set of bits having the first logic state; and means for generating a set of bit values corresponding to the determined number of bits.

18 . The apparatus of claim 15 , wherein:
the first logic state is associated with a logic state of 1.

19 . The apparatus of claim 15 , wherein:
the first logic state is associated with a logic state corresponding to a first set of threshold voltages.

20 . The apparatus of claim 19 , wherein:
the first set of threshold voltages are threshold voltages less than threshold voltages of a second set of threshold voltages associated with a second logic state; and the second logic state is associated with a logic state of 0.

Assignees

• Micron Technology Inc

Inventors

• Mirichigni Graziano
• Amato Paolo
• Pio Federico
• Orlando Alessandro
• Sforzin Marco

Classifications

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C13/003

  Cell access · CPC title