Resistive memory architectures with multiple memory cells per access device

Patent metadata

Field	Value
Publication number	US-2021005811-A1
Application number	US-202017018554-A
Country	US
Kind code	A1
Filing date	Sep 11, 2020
Priority date	May 31, 2007
Publication date	Jan 7, 2021
Grant date	—

Abstract

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

First claim

What is claimed is:

1 . An apparatus, comprising:
an access device comprising a gate and a drain; a dielectric that contacts at least a portion of the gate of the access device and at least a portion of the drain of the access device; a via extending through the dielectric and through at least a portion of the drain of the access device; and a deposited layer of material positioned within the via.

2 . The apparatus of claim 1 , further comprising:
one or more tungsten contacts positioned in the via and in contact with the deposited layer of material.

3 . The apparatus of claim 1 , further comprising:
one or more platinum contacts positioned in the via and in contact with the deposited layer of material.

4 . The apparatus of claim 1 , wherein the deposited layer of material comprises titanium silicide, titanium nitride, or a combination thereof.

5 . The apparatus of claim 1 , wherein the deposited layer of material comprises platinum, or platinum silicide, or a combination thereof.

6 . The apparatus of claim 1 , further comprising:
a word line in contact with the gate of the access device and the drain of the access device.

7 . The apparatus of claim 1 , wherein a bottom of the via is p-doped or n-doped.

8 . A memory device, comprising:
a first memory cell; an access device comprising a gate and a drain and operatively coupled with the first memory cell; and a rectifying device coupled with the first memory cell and the access device comprising:
a dielectric that contacts at least a portion of the gate of the access device and at least a portion of the drain of the access device;
a via extending through the dielectric and through at least a portion of the drain of the access device; and
a deposited layer of material positioned within the via.

9 . The memory device of claim 8 , wherein the rectifying device further comprises:
one or more tungsten contacts positioned in the via and in contact with the deposited layer of material.

10 . The memory device of claim 8 , wherein the rectifying device further comprises:
one or more platinum contacts positioned in the via and in contact with the deposited layer of material.

11 . The memory device of claim 8 , wherein the deposited layer of material comprises titanium silicide, or titanium nitride, or a combination thereof.

12 . The memory device of claim 8 , wherein the deposited layer of material comprises platinum, or platinum silicide, or a combination thereof.

13 . The memory device of claim 8 , further comprising:
a word line in contact with the gate of the access device and the drain of the access device.

14 . The memory device of claim 8 , wherein a bottom of the via is p-doped or n-doped.

15 . A system, comprising:
a first memory cell; an access device comprising a gate and a drain and operatively coupled with the first memory cell; and a rectifying device coupled with the first memory cell and the access device comprising:
a dielectric that contacts at least a portion of the gate of the access device and at least a portion of the drain of the access device;
a via extending through the dielectric and through at least a portion of the drain of the access device; and
a deposited layer of material positioned within the via.

16 . The system of claim 15 , wherein the rectifying device further comprises:
one or more tungsten contacts positioned in the via and in contact with the deposited layer of material.

17 . The system of claim 15 , wherein the rectifying device further comprises:
one or more platinum contacts positioned in the via and in contact with the deposited layer of material.

18 . The system of claim 15 , wherein the deposited layer of material comprises titanium silicide, or titanium nitride, or a combination thereof.

19 . The system of claim 15 , wherein the deposited layer of material comprises platinum, or platinum silicide, or a combination thereof.

20 . The system of claim 15 , wherein a bottom of the via is p-doped or n-doped.

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Liu Jun
• Violette Michael P

Classifications

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C16/00

  Erasable programmable read-only memories (G11C14/00 takes precedence) · CPC title

• G11C16/02 Primary

  electrically programmable · CPC title

• G11C2213/78

  Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title