Fabrication of gate all around device

Patent metadata

Field	Value
Publication number	US-2020403075-A1
Application number	US-202017006802-A
Country	US
Kind code	A1
Filing date	Aug 29, 2020
Priority date	Sep 28, 2017
Publication date	Dec 24, 2020
Grant date	—

Abstract

A device includes a nanowire, a gate dielectric layer, a gate electrode, a gate pickup metal layer, and a gate contact. The nanowire extends in a direction perpendicular to a top surface of a substrate. The gate dielectric layer laterally surrounds the nanowire. The gate electrode laterally surrounds the gate dielectric layer. The gate pickup metal layer is in contact with a bottom surface of the gate electrode and extends laterally past opposite sidewalls of the gate electrode. The gate contact is in contact with the gate pickup metal layer.

First claim

What is claimed is:

1 . A device comprising:
a nanowire extending in a direction perpendicular to a top surface of a substrate; a gate dielectric layer laterally surrounding the nanowire; a gate electrode laterally surrounding the gate dielectric layer; a gate pickup metal layer in contact with a bottom surface of the gate electrode and extending laterally past opposite sidewalls of the gate electrode; and a gate contact in contact with the gate pickup metal layer.

2 . The device of claim 1 , wherein the nanowire comprises an n-doped metal or a p-doped metal.

3 . The device of claim 1 , wherein the nanowire is free of P-N junction.

4 . The device of claim 1 , wherein the nanowire has a first source/drain region, a channel region above the first source/drain region, and a second source/drain region above the channel region, and wherein the first and second source/drain regions and the channel region have a same dopant type.

5 . The device of claim 1 , wherein the gate contact is also in contact with a sidewall of the gate electrode.

6 . The device of claim 5 , wherein an interface formed by the gate contact and the sidewall of the gate electrode extends at an obtuse angle from an interface formed by the gate contact and the gate pickup metal layer.

7 . The device of claim 5 , wherein the sidewall of the gate electrode in contact with the gate contact is tapered.

8 . The device of claim 1 , wherein the gate contact has a convex top.

9 . The device of claim 1 , wherein the nanowire has a bottom end lower than a bottom surface of the gate pickup metal layer.

10 . The device of claim 1 , further comprising:
a source/drain contact atop the nanowire, the source/drain contact has a top surface non-parallel with a top surface of the gate contact.

11 . A device comprising:
a source/drain pickup metal layer over a substrate; a nanowire over the source/drain pickup metal layer, the nanowire having a first source/drain region at a bottom portion of the nanowire, a second source/drain region at a top portion of the nanowire, and a sidewall laterally set back from a tapered sidewall of the source/drain pickup metal layer; a gate dielectric layer laterally surrounding the sidewall of the nanowire; a gate electrode laterally surrounding the gate dielectric layer; and a first source/drain contact in contact with the tapered sidewall of the source/drain pickup metal layer.

12 . The device of claim 11 , wherein the first source/drain contact has a convex top.

13 . The device of claim 12 , wherein an apex of the convex top of the first source/drain contact is higher than a top end of the nanowire.

14 . The device of claim 11 , further comprising:
a second source/drain contact over the top portion of the nanowire, wherein the second source/drain contact has a top surface non-parallel with a top surface of the first source/drain contact.

15 . The device of claim 14 , wherein the top surface of the second source/drain contact is higher than the top surface of the first source/drain contact.

16 . The device of claim 14 , wherein the second source/drain contact comprises a different material than the first source/drain contact.

17 . A device comprising:
a source/drain pickup metal layer over a substrate; an etch stop layer covering a first region of a top surface of the source/drain pickup metal layer, while not covering a second region of the top surface of the source/drain pickup metal layer; a source/drain contact in contact with the second region of the top surface of the source/drain pickup metal layer; a nanowire extending upwardly from a third region of the top surface of the source/drain pickup metal layer through the etch stop layer; and a gate electrode laterally surrounding the nanowire.

18 . The device of claim 17 , wherein the source/drain contact is also in contact with a sidewall of the etch stop layer.

19 . The device of claim 17 , wherein the etch stop layer laterally surrounds the nanowire and is below the gate electrode.

20 . The device of claim 17 , further comprising:
a gate contact electrically coupled to the gate electrode, wherein both the gate contact and the source/drain contact have convex tops.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Yung-Chih
• Liao Yu-Chieh
• Yang Tai-I
• Chen Hsin-Ping

Classifications

• H10D62/122

  oriented at angles to substrates, e.g. perpendicular to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6728

  Vertical TFTs · CPC title