Method and apparatus for implementing data transmission, electronic device, and computer-readable storage medium

Patent metadata

Field	Value
Publication number	US-2020401542-A1
Application number	US-202017007523-A
Country	US
Kind code	A1
Filing date	Aug 31, 2020
Priority date	May 31, 2018
Publication date	Dec 24, 2020
Grant date	—

Abstract

This application discloses a method and an apparatus, an electronic device, and a computer-readable storage medium for implementing data transmission. The method is executed by an electronic device providing a computing service, and is applied to execution of data transmission between two buses of different types, wherein one of the two buses is associated with an FPGA instance among multiple FPGA instances run by the computing service and the other of the two buses corresponds to an external device to the electronic device, the method including: obtaining an access instruction from an initiator through a first bus of the two buses for data read/write in a target, wherein the initiator and the target are associated with the first bus and a second bus of the two buses, and comprise one and the other of the FPGA instance and the external device, respectively; buffering the access instruction into an instruction storage area corresponding to the access instruction; and transmitting the access instruction buffered in the instruction storage area to the target continuously, and suspending transmission of the access instruction to the target once a flow control is imposed.

First claim

What is claimed is:

1 . A method for implementing data transmission, executed by an electronic device providing a computing service, the method being applied to execution of data transmission between two buses of different types, wherein one of the two buses is associated with an FPGA instance among multiple FPGA instances run by the computing service and the other of the two buses corresponds to an external device to the electronic device, the method comprising:
obtaining an access instruction from an initiator through a first bus of the two buses for data read/write in a target, wherein the initiator and the target are associated with the first bus and a second bus of the two buses, and comprise one and the other of the FPGA instance and the external device, respectively; buffering the access instruction into an instruction storage area corresponding to the access instruction; and transmitting the access instruction buffered in the instruction storage area to the target continuously, and suspending transmission of the access instruction to the target once a flow control is imposed.

2 . The method according to claim 1 , wherein transmitting the access instruction buffered in the instruction storage area continuously to the target comprises:
transmitting continuously, according to a clock cycle of transmitting the access instruction to the target, the access instruction buffered in the instruction storage area to the target, until receiving a flow control signal returned by the target.

3 . The method according to claim 1 , further comprising:
buffering read/write feedback data returned by the target into a data storage area corresponding to the access instruction; and transmitting the read/write feedback data buffered in the data storage area continuously to the initiator, until receiving a flow control signal returned by the initiator for the read/write feedback data.

4 . The method according to claim 3 , wherein transmitting the access instruction buffered in the instruction storage area to the target continuously, and suspending transmission of the access instruction to the target the once flow control is imposed comprises:
transmitting the access instruction buffered in the instruction storage area to the target continuously until receiving the flow control signal returned by the target, when the data storage area is not full.

5 . The method according to claim 1 , wherein obtaining the access instruction from the initiator through the first bus of the two buses for data read/write in the target comprises:
receiving an access request for data read/write from the initiator; and obtaining the access instruction corresponding to the access request according to a protocol conversion rule between the two buses.

6 . The method according to claim 5 , wherein receiving the access request for data read/write comprises:
receiving, through an AXI bus or a CCI-P bus corresponding to the FPGA instance, an access request initiated by the FPGA instance and used for performing data read/write in the external device.

7 . The method according to claim 5 , wherein receiving the access request for data read/write comprises:
receiving, through a CCI-P bus or an AXI bus corresponding to the external device, an access request initiated by the external device and used for performing data read/write in the FPGA instance.

8 . The method according to claim 5 , wherein obtaining the access instruction corresponding to the access request according to the protocol conversion rule between the two buses comprises:
determining validity of the access request according to identification information carried in the access request; and mapping, according to the protocol conversion rule between the two buses, the access request containing an address signal, to an access instruction containing a read/write address, when the access request is valid.

9 . The method according to claim 1 , wherein buffering the access instruction into the instruction storage area corresponding to the access instruction comprises:
writing continuously, according to the target and an instruction type indicated by the access instruction, the access instruction into an instruction storage area corresponding to the target and the instruction type, until the instruction storage area is full.

10 . An apparatus for implementing data transmission between two buses of different types, wherein one of the two buses is associated with an FPGA instance among multiple FPGA instances run by a computing service provided by the apparatus and the other of the two buses corresponds to an external device to the apparatus, the apparatus comprising a memory for storing computer readable instructions and a processor in communication with the memory, wherein the processor is configured to execute the computer readable instructions to cause the apparatus to:
obtain an access instruction from an initiator through a first bus of the two buses for data read/write in a target, wherein the initiator and the target are associated with the first bus and a second bus of the two buses, and comprise one and the other of the FPGA instance and the external device, respectively; buffer the access instruction into an instruction storage area corresponding to the access instruction; and transmit the access instruction buffered in the instruction storage area to the target continuously, and suspend transmission of the access instruction to the target once a flow control is imposed.

11 . The apparatus according to claim 10 , wherein, when the processor is configured to cause the apparatus to transmit the access instruction buffered in the instruction storage area continuously to the target, the processor is configured to cause the apparatus to:
transmit continuously, according to a clock cycle of transmitting the access instruction to the target, the access instruction buffered in the instruction storage area to the target, until receiving a flow control signal returned by the target.

12 . The apparatus according to claim 10 , wherein, when the processor executes the instructions, the processor is configured to further cause the apparatus to:
buffer read/write feedback data returned by the target into a data storage area corresponding to the access instruction; and transmit the read/write feedback data buffered in the data storage area continuously to the initiator, until receiving a flow control signal returned by the initiator for the read/write feedback data.

13 . The apparatus according to claim 12 , wherein, when the processor is configured to cause the apparatus to transmit the access instruction buffered in the instruction storage area to the target continuously, and suspend transmission of the access instruction to the target once the flow control is imposed, the processor is configured to cause the apparatus to:
transmit the access instruction buffered in the instruction storage area to the target continuously until receiving the flow control signal returned by the target, when the data storage area is not full.

14 . The apparatus according to claim 10 , wherein, when the processor is configured to cause the apparatus to obtain the access instruction from the initiator through the first bus of the two buses for data read/write in the target, the processor is configured to cause the apparatus to:
receive an access request for data read/write from the initiator; and obtain the access instruction corresponding to the access request according to a protocol conversion rule between the two buses.

15 . The apparatus according to claim 14 , wherein, when th

Assignees

• Tencent Tech Shenzhen Co Ltd

Inventors

• Li Jiaxin

Classifications

• G06F13/36 Primary

  for access to common bus or bus system · CPC title

• G06F13/4004

  Coupling between buses · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F2213/3852

  Converter between protocols · CPC title

• G06F13/38

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title