Multi-Pin-Wafer-Level-Chip-Scale-Packaging Solution for High Power Semiconductor Devices

Patent metadata

Field	Value
Publication number	US-2020395325-A1
Application number	US-202016995697-A
Country	US
Kind code	A1
Filing date	Aug 17, 2020
Priority date	Aug 25, 2017
Publication date	Dec 17, 2020
Grant date	—

Abstract

A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

First claim

1 . A method of fabricating a multi-pin wafer level chip scale package comprising:
providing a silicon wafer having a passivation layer thereon having openings therein to silicon pads on said silicon wafer; coating a first polymer layer on said passivation layer; and forming one or more metal traces contacting said silicon pads through openings in said first polymer layer in areas where low current connections are to be made and forming one or more metal blocks over and through vias contacting said silicon pads through openings in said first polymer layer in areas where high current connections are to be made, said forming said metal traces and said metal blocks comprising:
patterning said first polymer layer to form first openings to said silicon pads in said low current connection areas and to form vias to said silicon pads in said high current connection areas;
sputtering a redistribution layer (RDL) seed layer over said first polymer layer and in said first openings and vias;
plating a RDL layer on said RDL seed layer in said low current connection areas;
etching said RDL layer in said low current connection areas to form RDL traces;
thereafter forming RDL_VIAS in said high current connection areas;
thereafter depositing a second polymer layer over said RDL traces and RDL_VIAs and patterning said second polymer layer to provide second openings to said RDL_VIAS and to said RDL traces;
sputtering an under pillar metal (UPM) seed layer on said second polymer layer and within said second openings;
plating a UPM layer on said UPM seed layer in said low current areas wherein said UPM layer and said RDL traces together form said metal traces; and
plating solder pillars on and above said metal traces;
thereafter etching away said UPM layer not covered by said solder pillars;
thereafter sputtering an under block metal (UBM) seed layer within said second openings over said RDL_VIAs;
forming a UBM layer on said UBM seed layer in said high current connection areas wherein said RDL_VIA and said UBM layer together form said metal blocks; and
plating solder blocks on and above said metal blocks wherein said solder blocks are wider than said solder pillars and wherein a top surface of each of said solder pillars and solder blocks are in the same horizontal plane to complete said multi-pin wafer level chip scale package.

2 . The method according to claim 1 wherein in said areas where high current connections are to be made said solder blocks can conduct currents of greater than 2 A and wherein in areas where low current connections are to be made said solder pillars can conduct currents equal to or lower than 2 A.

3 . The method according to claim 1 wherein said forming RDL_VIAS in said high current connection areas comprises:
sputtering a RDL_VIA seed layer into said vias;
thereafter plating a RDL_VIA layer into and above said vias; and
etching said RDL_VIA layer to form RDL_VIAS in said high current connection areas; and'

wherein said forming said UBM layer comprises:
plating a UBM layer on said UBM seed layer in said high current connection areas wherein said RDL_VIA and said UBM layer together form said metal blocks;

and
after said plating said metal blocks, thereafter etching away said UBM layer not covered by said solder blocks.

4 . The method according to claim 1 wherein said forming said RDL_VIAS in said high current connection areas comprises:
etching away said RDL seed layer in said vias;
thereafter sputtering a RDL_VIA seed layer in said vias;
thereafter placing a RDL_VIA strip in said vias and etching away said RDL_VIA seed layer not covered by said RDL_VIA strip; and'

wherein said forming said UBM layer comprises:
placing a UBM strip on said RDL_VIA strip wherein said RDL_VIA strip in said vias and said UBM strip over said RDL strip in said vias form said metal blocks; and
after said plating said metal blocks, thereafter sawing and trimming away excess RDL_VIA and UBM strip material.

5 . The method according to claim 1 further comprising:
after said sputtering said redistribution layer (RDL) seed layer over said first polymer layer and in said first openings and vias, etching back said RDL seed layer in said low current connection areas to reduce RDL seed layer thickness;
after said sputtering said metal seed layer on said second polymer layer and within said second openings, etching back said metal seed layer in said low current connection areas to reduce metal seed layer thickness; and
after plating said UPM layer on said metal seed layer in said low current connection areas, etching back said UPM layer in said low current connection areas to form UPM traces and to reduce UPM thickness.

6 . The method according to claim 1 wherein said solder blocks and solder pillars are formed in a fan out wafer level chip scale package.

7 . The method according to claim 1 wherein said solder pillars have a height of at least 120 μm and wherein said solder blocks have a height of at least 100 μm and wherein said metal traces have a thickness of >=4 μm and <=25 μm and wherein said metal blocks have a thickness of >=25 μm and <=50 μm.

8 . A method of fabricating a multi-pin wafer level chip scale package comprising:
providing a silicon wafer having a passivation layer thereon having openings therein to silicon pads on said silicon wafer; coating a first polymer layer on said passivation layer; and forming one or more metal traces contacting said silicon pads through openings in said first polymer layer in areas where low current connections are to be made and forming one or more metal blocks over and through vias contacting said silicon pads through openings in said first polymer layer in areas where high current connections are to be made, said forming said metal traces and said metal blocks comprising:
patterning said first polymer layer to form first openings to said silicon pads in said low current connection areas and to form vias to said silicon pads in said high current connection areas;
sputtering a redistribution layer (RDL) seed layer over said first polymer layer and in said first openings and vias;
plating a RDL layer on said RDL seed layer in said low current connection areas;
etching said RDL layer in said low current connection areas to form RDL traces;
thereafter forming RDL_VIAS in said high current connection areas;
thereafter depositing a second polymer layer over said RDL traces and patterning said second polymer layer to provide second openings to said RDL_VIAs and to said RDL traces;
plating solder pillars on and above said RDL traces;
thereafter sputtering an under block metal (UBM) seed layer within said second openings over said RDL_VIAs;
forming a UBM layer on said UBM seed layer in said high current connection areas wherein said RDL_VIA and said UBM layer together form said metal blocks; and
plating solder blocks on and above said metal blocks wherein said solder blocks are wider than said solder pillars and wherein a top surface of each of said solder pillars and solder blocks are in the same horizontal plane to complete said multi-pin wafer level chip scale package.

9 . The method according to claim 8 wherein said forming RDL_VIAS in said high current connection areas comprises:
sputtering a RDL_VIA seed layer into said vias;
thereafter plating a RDL_VIA layer into and above said vias; and
etching said RDL_VIA layer to form RDL_VIAS in said high current connection areas; and'

wherein said forming said UBM layer comprises:
plating a UBM layer on said UBM seed layer in said high current connection areas wherein said RDL_VIA and said UBM layer together form said metal blocks;

and
after said plating said metal

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Mohammed Habeeb Mohiuddin
• Aiyandra Rajesh Subraya

Classifications

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title